pingche.syr

简易数字频率计

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_1_I3_0:O'
Delay:               3.675ns (Levels of Logic = 1)
  Source:            XLXI_10_a_0 (FF)
  Destination:       XLXI_10_Mtrien_COUNT_LOAD (FF)
  Source Clock:      XLXI_1_I3_0:O rising
  Destination Clock: XLXI_1_I3_0:O rising

  Data Path: XLXI_10_a_0 to XLXI_10_Mtrien_COUNT_LOAD
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              3   1.085   1.332  XLXI_10_a_0 (XLXI_10_a_0)
     LUT2:I1->O            2   0.549   0.000  XLXI_10__n00081 (XLXI_10__n0008)
     FDC:D                     0.709          XLXI_10_Mtrien_COUNT_LOAD
    ----------------------------------------
    Total                      3.675ns (2.343ns logic, 1.332ns route)
                                       (63.8% logic, 36.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_3_XLXI_5_COUT:Q'
Delay:               5.114ns (Levels of Logic = 6)
  Source:            XLXI_3_XLXI_6_D6_5 (FF)
  Destination:       XLXI_3_XLXI_6_D6_7 (FF)
  Source Clock:      XLXI_3_XLXI_5_COUT:Q rising
  Destination Clock: XLXI_3_XLXI_5_COUT:Q rising

  Data Path: XLXI_3_XLXI_6_D6_5 to XLXI_3_XLXI_6_D6_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_3_XLXI_6_D6_5 (XLXI_3_XLXI_6_D6_5)
     LUT4:I1->O            1   0.549   0.000  XLXI_3_XLXI_6__n00011 (XLXI_3_XLXI_6__n0001)
     MUXCY:S->O            1   0.659   0.000  XLXI_3_XLXI_6_D6_inst_cy_44 (XLXI_3_XLXI_6_D6_inst_cy_44)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_XLXI_6_D6_inst_cy_45 (XLXI_3_XLXI_6_D6_inst_cy_45)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_XLXI_6_D6_inst_cy_46 (XLXI_3_XLXI_6_D6_inst_cy_46)
     MUXCY:CI->O           0   0.042   0.000  XLXI_3_XLXI_6_D6_inst_cy_47 (XLXI_3_XLXI_6_D6_inst_cy_47)
     XORCY:CI->O           1   0.420   0.000  XLXI_3_XLXI_6_D6_inst_sum_46 (XLXI_3_XLXI_6_D6_inst_sum_46)
     FDCPE:D                   0.709          XLXI_3_XLXI_6_D6_7
    ----------------------------------------
    Total                      5.114ns (3.548ns logic, 1.566ns route)
                                       (69.4% logic, 30.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_3_XLXI_4_COUT:Q'
Delay:               5.114ns (Levels of Logic = 6)
  Source:            XLXI_3_XLXI_5_D5_5 (FF)
  Destination:       XLXI_3_XLXI_5_D5_7 (FF)
  Source Clock:      XLXI_3_XLXI_4_COUT:Q rising
  Destination Clock: XLXI_3_XLXI_4_COUT:Q rising

  Data Path: XLXI_3_XLXI_5_D5_5 to XLXI_3_XLXI_5_D5_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_3_XLXI_5_D5_5 (XLXI_3_XLXI_5_D5_5)
     LUT4:I1->O            2   0.549   0.000  XLXI_3_XLXI_5__n00021 (XLXI_3_XLXI_5__n0002)
     MUXCY:S->O            1   0.659   0.000  XLXI_3_XLXI_5_D5_inst_cy_44 (XLXI_3_XLXI_5_D5_inst_cy_44)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_XLXI_5_D5_inst_cy_45 (XLXI_3_XLXI_5_D5_inst_cy_45)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_XLXI_5_D5_inst_cy_46 (XLXI_3_XLXI_5_D5_inst_cy_46)
     MUXCY:CI->O           0   0.042   0.000  XLXI_3_XLXI_5_D5_inst_cy_47 (XLXI_3_XLXI_5_D5_inst_cy_47)
     XORCY:CI->O           1   0.420   0.000  XLXI_3_XLXI_5_D5_inst_sum_46 (XLXI_3_XLXI_5_D5_inst_sum_46)
     FDCPE:D                   0.709          XLXI_3_XLXI_5_D5_7
    ----------------------------------------
    Total                      5.114ns (3.548ns logic, 1.566ns route)
                                       (69.4% logic, 30.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_3_XLXI_3_COUT:Q'
Delay:               5.114ns (Levels of Logic = 6)
  Source:            XLXI_3_XLXI_4_D4_5 (FF)
  Destination:       XLXI_3_XLXI_4_D4_7 (FF)
  Source Clock:      XLXI_3_XLXI_3_COUT:Q rising
  Destination Clock: XLXI_3_XLXI_3_COUT:Q rising

  Data Path: XLXI_3_XLXI_4_D4_5 to XLXI_3_XLXI_4_D4_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_3_XLXI_4_D4_5 (XLXI_3_XLXI_4_D4_5)
     LUT4:I1->O            2   0.549   0.000  XLXI_3_XLXI_4__n00021 (XLXI_3_XLXI_4__n0002)
     MUXCY:S->O            1   0.659   0.000  XLXI_3_XLXI_4_D4_inst_cy_44 (XLXI_3_XLXI_4_D4_inst_cy_44)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_XLXI_4_D4_inst_cy_45 (XLXI_3_XLXI_4_D4_inst_cy_45)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_XLXI_4_D4_inst_cy_46 (XLXI_3_XLXI_4_D4_inst_cy_46)
     MUXCY:CI->O           0   0.042   0.000  XLXI_3_XLXI_4_D4_inst_cy_47 (XLXI_3_XLXI_4_D4_inst_cy_47)
     XORCY:CI->O           1   0.420   0.000  XLXI_3_XLXI_4_D4_inst_sum_46 (XLXI_3_XLXI_4_D4_inst_sum_46)
     FDCPE:D                   0.709          XLXI_3_XLXI_4_D4_7
    ----------------------------------------
    Total                      5.114ns (3.548ns logic, 1.566ns route)
                                       (69.4% logic, 30.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_3_XLXI_2_COUT:Q'
Delay:               5.114ns (Levels of Logic = 6)
  Source:            XLXI_3_XLXI_3_D3_5 (FF)
  Destination:       XLXI_3_XLXI_3_D3_7 (FF)
  Source Clock:      XLXI_3_XLXI_2_COUT:Q rising
  Destination Clock: XLXI_3_XLXI_2_COUT:Q rising

  Data Path: XLXI_3_XLXI_3_D3_5 to XLXI_3_XLXI_3_D3_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_3_XLXI_3_D3_5 (XLXI_3_XLXI_3_D3_5)
     LUT4:I1->O            2   0.549   0.000  XLXI_3_XLXI_3__n00021 (XLXI_3_XLXI_3__n0002)
     MUXCY:S->O            1   0.659   0.000  XLXI_3_XLXI_3_D3_inst_cy_44 (XLXI_3_XLXI_3_D3_inst_cy_44)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_XLXI_3_D3_inst_cy_45 (XLXI_3_XLXI_3_D3_inst_cy_45)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_XLXI_3_D3_inst_cy_46 (XLXI_3_XLXI_3_D3_inst_cy_46)
     MUXCY:CI->O           0   0.042   0.000  XLXI_3_XLXI_3_D3_inst_cy_47 (XLXI_3_XLXI_3_D3_inst_cy_47)
     XORCY:CI->O           1   0.420   0.000  XLXI_3_XLXI_3_D3_inst_sum_46 (XLXI_3_XLXI_3_D3_inst_sum_46)
     FDCPE:D                   0.709          XLXI_3_XLXI_3_D3_7
    ----------------------------------------
    Total                      5.114ns (3.548ns logic, 1.566ns route)
                                       (69.4% logic, 30.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_3_XLXI_1_COUT:Q'
Delay:               5.114ns (Levels of Logic = 6)
  Source:            XLXI_3_XLXI_2_D2_5 (FF)
  Destination:       XLXI_3_XLXI_2_D2_7 (FF)
  Source Clock:      XLXI_3_XLXI_1_COUT:Q rising
  Destination Clock: XLXI_3_XLXI_1_COUT:Q rising

  Data Path: XLXI_3_XLXI_2_D2_5 to XLXI_3_XLXI_2_D2_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_3_XLXI_2_D2_5 (XLXI_3_XLXI_2_D2_5)
     LUT4:I1->O            2   0.549   0.000  XLXI_3_XLXI_2__n00021 (XLXI_3_XLXI_2__n0002)
     MUXCY:S->O            1   0.659   0.000  XLXI_3_XLXI_2_D2_inst_cy_44 (XLXI_3_XLXI_2_D2_inst_cy_44)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_XLXI_2_D2_inst_cy_45 (XLXI_3_XLXI_2_D2_inst_cy_45)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_XLXI_2_D2_inst_cy_46 (XLXI_3_XLXI_2_D2_inst_cy_46)
     MUXCY:CI->O           0   0.042   0.000  XLXI_3_XLXI_2_D2_inst_cy_47 (XLXI_3_XLXI_2_D2_inst_cy_47)
     XORCY:CI->O           1   0.420   0.000  XLXI_3_XLXI_2_D2_inst_sum_46 (XLXI_3_XLXI_2_D2_inst_sum_46)
     FDCPE:D                   0.709          XLXI_3_XLXI_2_D2_7
    ----------------------------------------
    Total                      5.114ns (3.548ns logic, 1.566ns route)
                                       (69.4% logic, 30.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_13:O'
Delay:               5.114ns (Levels of Logic = 6)
  Source:            XLXI_3_XLXI_1_D1_1 (FF)
  Destination:       XLXI_3_XLXI_1_D1_3 (FF)
  Source Clock:      XLXI_13:O rising
  Destination Clock: XLXI_13:O rising

  Data Path: XLXI_3_XLXI_1_D1_1 to XLXI_3_XLXI_1_D1_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_3_XLXI_1_D1_1 (XLXI_3_XLXI_1_D1_1)
     LUT4:I1->O            2   0.549   0.000  XLXI_3_XLXI_1__n00021 (XLXI_3_XLXI_1__n0002)
     MUXCY:S->O            1   0.659   0.000  XLXI_3_XLXI_1_D1_inst_cy_39 (XLXI_3_XLXI_1_D1_inst_cy_39)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_XLXI_1_D1_inst_cy_40 (XLXI_3_XLXI_1_D1_inst_cy_40)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_XLXI_1_D1_inst_cy_41 (XLXI_3_XLXI_1_D1_inst_cy_41)
     MUXCY:CI->O           0   0.042   0.000  XLXI_3_XLXI_1_D1_inst_cy_42 (XLXI_3_XLXI_1_D1_inst_cy_42)
     XORCY:CI->O           1   0.420   0.000  XLXI_3_XLXI_1_D1_inst_sum_42 (XLXI_3_XLXI_1_D1_inst_sum_42)
     FDCPE:D                   0.709          XLXI_3_XLXI_1_D1_3
    ----------------------------------------
    Total                      5.114ns (3.548ns logic, 1.566ns route)
                                       (69.4% logic, 30.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_2_I3_0:O'
Delay:               4.593ns (Levels of Logic = 1)
  Source:            XLXI_5_i_0 (FF)
  Destination:       XLXI_5_i_2 (FF)
  Source Clock:      XLXI_2_I3_0:O rising
  Destination Clock: XLXI_2_I3_0:O rising

  Data Path: XLXI_5_i_0 to XLXI_5_i_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             13   1.085   2.250  XLXI_5_i_0 (XLXI_5_i_0)
     LUT3:I1->O            1   0.549   0.000  XLXI_5_i_Madd__n0000_Mxor_Result<2>_Result1 (XLXI_5_i__n0000<2>)
     FD:D                      0.709          XLXI_5_i_2
    ----------------------------------------
    Total                      4.593ns (2.343ns logic, 2.250ns route)
                                       (51.0% logic, 49.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               9.541ns (Levels of Logic = 3)
  Source:            XLXI_1_a_19 (FF)
  Destination:       XLXI_1_a_22 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_1_a_19 to XLXI_1_a_22
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              8   1.085   1.845  XLXI_1_a_19 (XLXI_1_a_19)
     LUT4:I0->O            1   0.549   1.035  XLXI_1__n000176 (CHOICE504)
     LUT3_D:I0->O          1   0.549   1.035  XLXI_1__n0001106_SW0 (N9715)
     LUT4:I3->O           12   0.549   2.160  XLXI_1__n0001106_1 (XLXI_1__n0001106_1)
     FDR:R                     0.734          XLXI_1_a_9
    ----------------------------------------
    Total                      9.541ns (3.466ns logic, 6.075ns route)
                                       (36.3% logic, 63.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_1_I3_0:O'
Offset:              5.082ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       XLXI_10_a_1 (FF)
  Destination Clock: XLXI_1_I3_0:O rising

  Data Path: reset to XLXI_10_a_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             6   0.776   1.665  reset_IBUF (reset_IBUF)
     LUT1:I0->O            2   0.549   1.206  XLXI_10_a_ClkEn_INV1 (XLXI_10_a_N526)
     FDE:CE                    0.886          XLXI_10_a_0
    ----------------------------------------
    Total                      5.082ns (2.211ns logic, 2.871ns route)
                                       (43.5% logic, 56.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_2_I3_0:O'
Offset:              7.913ns (Levels of Logic = 1)
  Source:            XLXI_5_i_1 (FF)
  Destination:       wx<1> (PAD)
  Source Clock:      XLXI_2_I3_0:O rising

  Data Path: XLXI_5_i_1 to wx<1>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              12   1.085   2.160  XLXI_5_i_1 (XLXI_5_i_1)
     OBUF:I->O                 4.668          wx_1_OBUF (wx<1>)
    ----------------------------------------
    Total                      7.913ns (5.753ns logic, 2.160ns route)
                                       (72.7% logic, 27.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_9__n00011:O'
Offset:              6.897ns (Levels of Logic = 1)
  Source:            XLXI_9_Q_6 (LATCH)
  Destination:       seg<6> (PAD)
  Source Clock:      XLXI_9__n00011:O falling

  Data Path: XLXI_9_Q_6 to seg<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   1.194   1.035  XLXI_9_Q_6 (XLXI_9_Q_6)
     OBUF:I->O                 4.668          seg_6_OBUF (seg<6>)
    ----------------------------------------
    Total                      6.897ns (5.862ns logic, 1.035ns route)
                                       (85.0% logic, 15.0% route)

=========================================================================
CPU : 6.42 / 7.75 s | Elapsed : 7.00 / 8.00 s
 
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Total memory usage is 73656 kilobytes