pingche.syr

简易数字频率计

    Found 1-bit register for signal <Mtridata_COUNT_LOAD> created at line 28.
    Found 1-bit register for signal <Mtrien_COUNT_EN> created at line 27.
    Found 1-bit register for signal <Mtrien_COUNT_LOAD> created at line 28.
    Summary:
	inferred   7 D-type flip-flop(s).
	inferred   2 Tristate(s).
Unit <kz2> synthesized.


Synthesizing Unit <ymq>.
    Related source file is E:/VHDL/past/pingche/ymq.vhdl.
WARNING:Xst:737 - Found 7-bit latch for signal <Q>.
Unit <ymq> synthesized.


Synthesizing Unit <szq>.
    Related source file is E:/VHDL/past/pingche/xzq.vhdl.
Unit <szq> synthesized.


Synthesizing Unit <scq>.
    Related source file is E:/VHDL/past/pingche/scq.vhdl.
WARNING:Xst:1778 - Inout <Q1> is assigned but never used.
WARNING:Xst:1778 - Inout <Q2> is assigned but never used.
WARNING:Xst:1778 - Inout <Q3> is assigned but never used.
WARNING:Xst:1778 - Inout <Q4> is assigned but never used.
WARNING:Xst:1778 - Inout <Q5> is assigned but never used.
WARNING:Xst:1778 - Inout <Q6> is assigned but never used.
WARNING:Xst:737 - Found 4-bit latch for signal <Q1>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q2>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q3>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q4>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q5>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q6>.
Unit <scq> synthesized.


Synthesizing Unit <s_6>.
    Related source file is E:/VHDL/past/pingche/s_6.vhdl.
    Found 3-bit up counter for signal <i>.
    Summary:
	inferred   1 Counter(s).
Unit <s_6> synthesized.


Synthesizing Unit <jsq>.
    Related source file is E:/VHDL/past/pingche/jsq.vhf.
Unit <jsq> synthesized.


Synthesizing Unit <fpq2ms>.
    Related source file is E:/VHDL/past/pingche/fpq2ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 15-bit comparator lessequal for signal <$n0002>.
    Found 15-bit comparator greatequal for signal <$n0007>.
    Found 15-bit comparator lessequal for signal <$n0008>.
    Found 15-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq2ms> synthesized.


Synthesizing Unit <fpq1s>.
    Related source file is E:/VHDL/past/pingche/fpq1s.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 24-bit comparator lessequal for signal <$n0002>.
    Found 24-bit comparator greatequal for signal <$n0007>.
    Found 24-bit comparator lessequal for signal <$n0008>.
    Found 24-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq1s> synthesized.


Synthesizing Unit <pingche>.
    Related source file is E:/VHDL/past/pingche/pingche.vhf.
Unit <pingche> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 11
 4-bit up counter                  : 6
 24-bit up counter                 : 1
 15-bit up counter                 : 1
 3-bit up counter                  : 3
# Registers                        : 18
 1-bit register                    : 17
 2-bit register                    : 1
# Latches                          : 7
 4-bit latch                       : 6
 7-bit latch                       : 1
# Comparators                      : 6
 24-bit comparator lessequal       : 2
 24-bit comparator greatequal      : 1
 15-bit comparator lessequal       : 2
 15-bit comparator greatequal      : 1
# Multiplexers                     : 3
 1-bit 2-to-1 multiplexer          : 3
# Tristates                        : 4
 1-bit tristate buffer             : 4

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch a_0 hinder the constant cleaning in the block kz2.
   You should achieve better results by setting this init to 0.
WARNING:Xst:1426 - The value init of the FF/Latch a_1 hinder the constant cleaning in the block kz2.
   You should achieve better results by setting this init to 1.
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <pingche> ...

Optimizing unit <szq> ...

Optimizing unit <fpq1s> ...

Optimizing unit <fpq2ms> ...

Optimizing unit <ymq> ...

Optimizing unit <div5freq> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
WARNING:Xst:382 - Register XLXI_10_Mtrien_COUNT_EN is equivalent to XLXI_10_Mtrien_COUNT_LOAD
Found area constraint ratio of 100 (+ 5) on block pingche, actual ratio is 16.
WARNING:Xst:382 - Register XLXI_10_Mtrien_COUNT_EN is equivalent to XLXI_10_Mtrien_COUNT_LOAD
FlipFlop XLXI_5_i_0 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : pingche.ngr
Top Level Output File Name         : pingche
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 13

Macro Statistics :
# Registers                        : 23
#      1-bit register              : 17
#      2-bit register              : 1
#      24-bit register             : 5
# Counters                         : 6
#      4-bit up counter            : 6
# Multiplexers                     : 3
#      2-to-1 multiplexer          : 3
# Tristates                        : 4
#      1-bit tristate buffer       : 4
# Adders/Subtractors               : 5
#      24-bit adder                : 5
# Comparators                      : 6
#      15-bit comparator greatequal: 1
#      15-bit comparator lessequal : 2
#      24-bit comparator greatequal: 1
#      24-bit comparator lessequal : 2

Cell Usage :
# BELS                             : 379
#      AND2                        : 1
#      GND                         : 1
#      LUT1                        : 59
#      LUT1_L                      : 15
#      LUT2                        : 24
#      LUT2_L                      : 15
#      LUT3                        : 14
#      LUT3_D                      : 1
#      LUT3_L                      : 1
#      LUT4                        : 56
#      LUT4_D                      : 1
#      LUT4_L                      : 2
#      MUXCY                       : 127
#      VCC                         : 1
#      XORCY                       : 61
# FlipFlops/Latches                : 123
#      FD                          : 3
#      FDC                         : 12
#      FDC_1                       : 1
#      FDCPE                       : 24
#      FDE                         : 7
#      FDP                         : 1
#      FDR                         : 42
#      FDS                         : 2
#      LD                          : 31
# Tri-States                       : 4
#      BUFT                        : 4
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 2
#      OBUF                        : 10
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                     130  out of    768    16%  
 Number of Slice Flip Flops:           123  out of   1536     8%  
 Number of 4 input LUTs:               188  out of   1536    12%  
 Number of bonded IOBs:                 12  out of     96    12%  
 Number of TBUFs:                        4  out of    768     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXN_18(XLXI_10_I7_0:O)            | NONE(*)(XLXI_6_Q3_1)   | 24    |
XLXN_1(XLXI_1_I3_0:O)              | NONE(*)(XLXI_10_a_0)   | 7     |
XLXI_3_XLXI_5_COUT:Q               | NONE                   | 4     |
XLXI_3_XLXI_4_COUT:Q               | NONE                   | 5     |
XLXI_3_XLXI_3_COUT:Q               | NONE                   | 5     |
XLXI_3_XLXI_2_COUT:Q               | NONE                   | 5     |
XLXI_3_XLXI_1_COUT:Q               | NONE                   | 5     |
XLXN_25(XLXI_13:O)                 | NONE(*)(XLXI_3_XLXI_1_D1_1)| 5     |
XLXN_22(XLXI_2_I3_0:O)             | NONE(*)(XLXI_5_i_0)    | 4     |
clk                                | BUFGP                  | 52    |
XLXI_9__n0001(XLXI_9__n00011:O)    | NONE(*)(XLXI_9_Q_3)    | 7     |
-----------------------------------+------------------------+-------+
(*) These 5 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.541ns (Maximum Frequency: 104.811MHz)
   Minimum input arrival time before clock: 5.082ns
   Maximum output required time after clock: 7.913ns
   Maximum combinational path delay: No path found