qdkz.syr

四人抢答器的实现

Optimizing unit <xzq3> ...

Optimizing unit <djs2> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Register XLXI_8_wx_1 equivalent to XLXI_8_wx_3 has been removed
Register XLXI_8_wx_0 equivalent to XLXI_8_wx_3 has been removed
Register XLXI_8_wx_4 equivalent to XLXI_8_wx_3 has been removed
Register XLXI_8_wx_2 equivalent to XLXI_8_wx_3 has been removed
Found area constraint ratio of 100 (+ 5) on block qdkz, actual ratio is 14.
Latch XLXI_8_wx_3 has been replicated 4 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : qdkz.ngr
Top Level Output File Name         : qdkz
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 24

Macro Statistics :
# ROMs                             : 1
#      16x8-bit ROM                : 1
# Registers                        : 22
#      1-bit register              : 13
#      26-bit register             : 7
#      4-bit register              : 2
# Tristates                        : 2
#      1-bit tristate buffer       : 2
# Adders/Subtractors               : 7
#      26-bit adder                : 7
# Comparators                      : 8
#      12-bit comparator greatequal: 1
#      12-bit comparator lessequal : 2
#      2-bit comparator less       : 2
#      26-bit comparator greatequal: 1
#      26-bit comparator lessequal : 2

Cell Usage :
# BELS                             : 339
#      AND4                        : 1
#      GND                         : 1
#      LUT1                        : 73
#      LUT1_L                      : 13
#      LUT2                        : 31
#      LUT2_L                      : 13
#      LUT3                        : 13
#      LUT4                        : 33
#      LUT4_D                      : 5
#      MUXCY                       : 108
#      MUXF5                       : 3
#      VCC                         : 1
#      XORCY                       : 44
# FlipFlops/Latches                : 82
#      FD                          : 3
#      FDC                         : 5
#      FDC_1                       : 1
#      FDE                         : 10
#      FDR                         : 40
#      FDRE                        : 9
#      FDS                         : 2
#      FDSE                        : 4
#      LD                          : 8
# Tri-States                       : 2
#      BUFT                        : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 23
#      IBUF                        : 6
#      OBUF                        : 17
# Logical                          : 1
#      NOR2                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                     121  out of    768    15%  
 Number of Slice Flip Flops:            82  out of   1536     5%  
 Number of 4 input LUTs:               181  out of   1536    11%  
 Number of bonded IOBs:                 23  out of     96    23%  
 Number of TBUFs:                        2  out of    768     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_4_q:Q                         | NONE                   | 5     |
XLXI_8__n0010(XLXI_8__n00101:O)    | NONE(*)(XLXI_8_wx_6)   | 8     |
XLXN_27(XLXI_5_I3_0:O)             | NONE(*)(XLXI_47_q)     | 23    |
XLXN_18(XLXI_25:O)                 | NONE(*)(XLXI_4_q)      | 1     |
XLXN_1(XLXI_3_I3_0:O)              | NONE(*)(XLXI_7_cnt_0)  | 3     |
clk                                | BUFGP                  | 42    |
-----------------------------------+------------------------+-------+
(*) These 4 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.631ns (Maximum Frequency: 103.831MHz)
   Minimum input arrival time before clock: 6.036ns
   Maximum output required time after clock: 17.398ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_5_I3_0:O'
Delay:               7.506ns (Levels of Logic = 2)
  Source:            XLXI_2_ll_0 (FF)
  Destination:       XLXI_2_ll_0 (FF)
  Source Clock:      XLXI_5_I3_0:O rising
  Destination Clock: XLXI_5_I3_0:O rising

  Data Path: XLXI_2_ll_0 to XLXI_2_ll_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDSE:C->Q             3   1.085   1.332  XLXI_2_ll_0 (XLXI_2_ll_0)
     LUT4_D:I0->O          6   0.549   1.665  XLXI_2__n00041 (XLXI_2__n0004)
     LUT2:I0->O            4   0.549   1.440  XLXI_2__n00101 (XLXI_2__n0010)
     FDSE:CE                   0.886          XLXI_2_ll_3
    ----------------------------------------
    Total                      7.506ns (3.069ns logic, 4.437ns route)
                                       (40.9% logic, 59.1% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_3_I3_0:O'
Delay:               5.043ns (Levels of Logic = 1)
  Source:            XLXI_7_cnt_0 (FF)
  Destination:       XLXI_7_cnt_2 (FF)
  Source Clock:      XLXI_3_I3_0:O rising
  Destination Clock: XLXI_3_I3_0:O rising

  Data Path: XLXI_7_cnt_0 to XLXI_7_cnt_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             18   1.085   2.700  XLXI_7_cnt_0 (XLXI_7_cnt_0)
     LUT3:I1->O            1   0.549   0.000  XLXI_7_cnt_Madd__n0000_Mxor_Result<2>_Result1 (XLXI_7_cnt__n0000<2>)
     FD:D                      0.709          XLXI_7_cnt_2
    ----------------------------------------
    Total                      5.043ns (2.343ns logic, 2.700ns route)
                                       (46.5% logic, 53.5% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               9.631ns (Levels of Logic = 3)
  Source:            XLXI_5_count_18 (FF)
  Destination:       XLXI_5_count_24 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_5_count_18 to XLXI_5_count_24
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              8   1.085   1.845  XLXI_5_count_18 (XLXI_5_count_18)
     LUT4:I0->O            1   0.549   1.035  XLXI_5__n000158 (CHOICE413)
     LUT4_D:I0->O          1   0.549   1.035  XLXI_5__n000199 (CHOICE427)
     LUT4:I3->O           13   0.549   2.250  XLXI_5__n0001115_1 (XLXI_5__n0001115_1)
     FDR:R                     0.734          XLXI_5_count_9
    ----------------------------------------
    Total                      9.631ns (3.466ns logic, 6.165ns route)
                                       (36.0% logic, 64.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_4_q:Q'
Offset:              2.691ns (Levels of Logic = 1)
  Source:            d1 (PAD)
  Destination:       XLXI_6_q1 (FF)
  Destination Clock: XLXI_4_q:Q rising

  Data Path: d1 to XLXI_6_q1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.776   1.206  d1_IBUF (d1_IBUF)
     FDC:D                     0.709          XLXI_6_q1
    ----------------------------------------
    Total                      2.691ns (1.485ns logic, 1.206ns route)
                                       (55.2% logic, 44.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_5_I3_0:O'
Offset:              6.036ns (Levels of Logic = 2)
  Source:            en (PAD)
  Destination:       XLXI_2_l_3 (FF)
  Destination Clock: XLXI_5_I3_0:O rising

  Data Path: en to XLXI_2_l_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            10   0.776   1.980  en_IBUF (en_IBUF)
     LUT1:I0->O            8   0.549   1.845  XLXI_2_l_N4311 (XLXI_2_l_N431)
     FDE:CE                    0.886          XLXI_2_l_0
    ----------------------------------------
    Total                      6.036ns (2.211ns logic, 3.825ns route)
                                       (36.6% logic, 63.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_5_I3_0:O'
Offset:              12.260ns (Levels of Logic = 4)
  Source:            XLXI_2_l_0 (FF)
  Destination:       q<6> (PAD)
  Source Clock:      XLXI_5_I3_0:O rising

  Data Path: XLXI_2_l_0 to q<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   1.085   1.035  XLXI_2_l_0 (XLXI_2_l_0)
     LUT4:I0->O            1   0.549   1.035  XLXI_8_q<0>63 (CHOICE301)
     LUT4:I3->O            7   0.549   1.755  XLXI_8_q<0>65 (XLXN_3<0>)
     LUT4:I0->O            1   0.549   1.035  XLXI_9_Mrom_Q_inst_lut4_01 (q_0_OBUF)
     OBUF:I->O                 4.668          q_0_OBUF (q<0>)
    ----------------------------------------
    Total                     12.260ns (7.400ns logic, 4.860ns route)
                                       (60.4% logic, 39.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_3_I3_0:O'
Offset:              17.398ns (Levels of Logic = 7)
  Source:            XLXI_7_cnt_0 (FF)
  Destination:       q<6> (PAD)
  Source Clock:      XLXI_3_I3_0:O rising

  Data Path: XLXI_7_cnt_0 to q<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             18   1.085   2.700  XLXI_7_cnt_0 (XLXI_7_cnt_0)
     LUT4:I0->O            1   0.549   1.035  XLXI_8_q<2>28 (CHOICE316)
     LUT2:I0->O            1   0.549   1.035  XLXI_8_q<2>30 (CHOICE317)
     LUT4:I3->O            1   0.549   1.035  XLXI_8_q<2>42 (CHOICE318)
     LUT4:I2->O            1   0.549   0.000  XLXI_8_q<2>97_G (N8259)
     MUXF5:I1->O           7   0.305   1.755  XLXI_8_q<2>97 (XLXN_3<2>)
     LUT4:I2->O            1   0.549   1.035  XLXI_9_Mrom_Q_inst_lut4_01 (q_0_OBUF)
     OBUF:I->O                 4.668          q_0_OBUF (q<0>)
    ----------------------------------------
    Total                     17.398ns (8.803ns logic, 8.595ns route)
                                       (50.6% logic, 49.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_4_q:Q'
Offset:              16.363ns (Levels of Logic = 7)
  Source:            XLXI_6_q2 (FF)
  Destination:       q<6> (PAD)
  Source Clock:      XLXI_4_q:Q rising

  Data Path: XLXI_6_q2 to q<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              6   1.085   1.665  XLXI_6_q2 (XLXI_6_q2)
     LUT4:I1->O            1   0.549   1.035  XLXI_8_q<2>28 (CHOICE316)
     LUT2:I0->O            1   0.549   1.035  XLXI_8_q<2>30 (CHOICE317)
     LUT4:I3->O            1   0.549   1.035  XLXI_8_q<2>42 (CHOICE318)
     LUT4:I2->O            1   0.549   0.000  XLXI_8_q<2>97_G (N8259)
     MUXF5:I1->O           7   0.305   1.755  XLXI_8_q<2>97 (XLXN_3<2>)
     LUT4:I2->O            1   0.549   1.035  XLXI_9_Mrom_Q_inst_lut4_01 (q_0_OBUF)
     OBUF:I->O                 4.668          q_0_OBUF (q<0>)
    ----------------------------------------
    Total                     16.363ns (8.803ns logic, 7.560ns route)
                                       (53.8% logic, 46.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_8__n00101:O'
Offset:              6.897ns (Levels of Logic = 1)
  Source:            XLXI_8_wx_7 (LATCH)
  Destination:       wx<7> (PAD)
  Source Clock:      XLXI_8__n00101:O falling

  Data Path: XLXI_8_wx_7 to wx<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   1.194   1.035  XLXI_8_wx_7 (XLXI_8_wx_7)
     OBUF:I->O                 4.668          wx_7_OBUF (wx<7>)
    ----------------------------------------
    Total                      6.897ns (5.862ns logic, 1.035ns route)
                                       (85.0% logic, 15.0% route)

=========================================================================
CPU : 5.52 / 7.28 s | Elapsed : 6.00 / 7.00 s
 
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Total memory usage is 60524 kilobytes