xzq3.syr

四人抢答器的实现

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: xzq3.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : xzq3.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : xzq3
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : xzq3
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : xzq3.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/VHDL/waitpast/qiangdaqi4ren/xzq3.vhdl in Library work.
Architecture behavioral of Entity xzq3 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <xzq3> (Architecture <behavioral>).
Entity <xzq3> analyzed. Unit <xzq3> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <xzq3>.
    Related source file is E:/VHDL/waitpast/qiangdaqi4ren/xzq3.vhdl.
WARNING:Xst:737 - Found 8-bit latch for signal <wx>.
Unit <xzq3> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Latches                          : 1
 8-bit latch                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <xzq3> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Register wx_4 equivalent to wx_3 has been removed
Register wx_3 equivalent to wx_1 has been removed
Register wx_2 equivalent to wx_1 has been removed
Register wx_1 equivalent to wx_0 has been removed
Found area constraint ratio of 100 (+ 5) on block xzq3, actual ratio is 1.
Latch wx_0 has been replicated 4 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : xzq3.ngr
Top Level Output File Name         : xzq3
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 27

Cell Usage :
# BELS                             : 16
#      LUT2                        : 2
#      LUT3                        : 6
#      LUT4                        : 4
#      MUXF5                       : 4
# FlipFlops/Latches                : 8
#      LD                          : 8
# IO Buffers                       : 27
#      IBUF                        : 15
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                       9  out of    768     1%  
 Number of Slice Flip Flops:             8  out of   1536     0%  
 Number of 4 input LUTs:                12  out of   1536     0%  
 Number of bonded IOBs:                 27  out of     96    28%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0010(_n00101:O)                  | NONE(*)(wx_0)          | 8     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: 4.194ns
   Maximum output required time after clock: 6.897ns
   Maximum combinational path delay: 9.503ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00101:O'
Offset:              4.194ns (Levels of Logic = 2)
  Source:            sel<2> (PAD)
  Destination:       wx_5 (LATCH)
  Destination Clock: _n00101:O falling

  Data Path: sel<2> to wx_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            12   0.776   2.160  sel_2_IBUF (sel_2_IBUF)
     LUT2:I1->O            1   0.549   0.000  _n0001<7>1 (_n0001<7>)
     LD:D                      0.709          wx_7
    ----------------------------------------
    Total                      4.194ns (2.034ns logic, 2.160ns route)
                                       (48.5% logic, 51.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00101:O'
Offset:              6.897ns (Levels of Logic = 1)
  Source:            wx_7 (LATCH)
  Destination:       wx<7> (PAD)
  Source Clock:      _n00101:O falling

  Data Path: wx_7 to wx<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   1.194   1.035  wx_7 (wx_7)
     OBUF:I->O                 4.668          wx_7_OBUF (wx<7>)
    ----------------------------------------
    Total                      6.897ns (5.862ns logic, 1.035ns route)
                                       (85.0% logic, 15.0% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               9.503ns (Levels of Logic = 4)
  Source:            sel<2> (PAD)
  Destination:       q<3> (PAD)

  Data Path: sel<2> to q<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            12   0.776   2.160  sel_2_IBUF (sel_2_IBUF)
     LUT3:I2->O            1   0.549   0.000  q<0>25_F (N1352)
     MUXF5:I0->O           1   0.315   1.035  q<0>25 (q_0_OBUF)
     OBUF:I->O                 4.668          q_0_OBUF (q<0>)
    ----------------------------------------
    Total                      9.503ns (6.308ns logic, 3.195ns route)
                                       (66.4% logic, 33.6% route)

=========================================================================
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Total memory usage is 56428 kilobytes