cont.vhdl

8*8点阵的实现

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cont is
    Port ( ch : in std_logic_vector(1 downto 0);
           sel : in std_logic_vector(2 downto 0);
           q : out std_logic_vector(7 downto 0));
end cont;

architecture Behavioral of cont is

begin
  process(ch,sel)
  begin
     case ch is
	    when"00"=>
	      case sel is
		     when"001"=>q<="00000111";	--从这个方向（右向左）看过去，以最左边为轴，对折过去就是点阵的显示效果
	        when"010"=>q<="00011100";
	        when"011"=>q<="01110000";
		     when"100"=>q<="11000000";
	        when"101"=>q<="11000000";
	        when"110"=>q<="01110000";
		     when"111"=>q<="00011100";
			  when"000"=>q<="00000111";
			  when others=>null;
		 end case;
	    when"01"=>
	      	case sel is
		       when"001"=>q<="00000000";
	          when"010"=>q<="11111111";
		 	    when"011"=>q<="11111111";
			    when"100"=>q<="00011000";
	          when"101"=>q<="00011000";
	          when"110"=>q<="11111111";
			    when"111"=>q<="11111111";
			    when"000"=>q<="00000000";
			   when others=>null;
		 end case;
	    when"10"=>
	      	case sel is
		     when"001"=>q<="00000000";
	        when"010"=>q<="00111100";
			  when"011"=>q<="01100110";
			  when"100"=>q<="11000011";
	        when"101"=>q<="11000011";
	        when"110"=>q<="11111111";
			  when"111"=>q<="11111111";
			  when"000"=>q<="00000000";
			  when others=>null;
		 end case;
	    when"11"=>
	      	case sel is
		     when"001"=>q<="00000000";
	        when"010"=>q<="11100000";
			  when"011"=>q<="11100000";
			  when"100"=>q<="11000000";
	        when"101"=>q<="11000000";
	        when"110"=>q<="11111111";
			  when"111"=>q<="11111111";
			  when"000"=>q<="00000000";
			  when others=>null;
		end case;
		when others=>null;
	   end case;
	end process;
end Behavioral;