__projnav.log

8*8点阵的实现

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Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dianzheng/chw.vhdl in Library work.
Entity <chw> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dianzheng/cnta.vhdl in Library work.
Entity <cnta> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dianzheng/cont.vhdl in Library work.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 25. String Literal
   "11000000" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 26. String Literal
   "00110000" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 27. String Literal
   "00001100" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 28. String Literal
   "00000011" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 29. String Literal
   "00000011" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 30. String Literal
   "00001100" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 31. String Literal
   "00110000" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 32. String Literal
   "11000000" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 37. String Literal
   "00000000" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 38. String Literal
   "11111111" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 39. String Literal
   "11111111" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 40. String Literal
   "00011000" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 41. String Literal
   "00011000" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 42. String Literal
   "11111111" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 43. String Literal
   "11111111" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 44. String Literal
   "00000000" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 49. String Literal
   "00000000" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 50. String Literal
   "11111111" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 51. String Literal
   "11000011" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 52. String Literal
   "11000011" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 53. String Literal
   "01100110" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 54. String Literal
   "01100110" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 55. String Literal
   "00111100" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 56. String Literal
   "00000000" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 61. String Literal
   "00000000" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 62. String Literal
   "11111111" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 63. String Literal
   "00000011" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 64. String Literal
   "11000011" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 65. String Literal
   "00000011" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 66. String Literal
   "00000011" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 67. String Literal
   "00000111" is not of size 16.
ERROR:HDLParsers:3384 - e:/vhdl/dianzheng/cont.vhdl Line 68. String Literal
   "00000000" is not of size 16.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dianzheng/cont.vhdl in Library work.
Entity <cont> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dianzheng/fpq10ms.vhdl in Library work.
Entity <fpq10ms> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dianzheng/cnta.vhdl in Library work.
Entity <cnta> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
ERROR:DesignEntry:20 - Pin "q(2:0)" is connected to a bus of a different width.
ERROR:DesignEntry:20 - Pin "sel(2:0)" is connected to a bus of a different
   width.
Error: 
Process "View VHDL Functional Model" did not complete.


Project Navigator Auto-Make Log File
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Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 55
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/vhdl/dianzheng/chw.vhdl in Library work.
Architecture behavioral of Entity chw is up to date.
Compiling vhdl file e:/vhdl/dianzheng/cnta.vhdl in Library work.
Architecture behavioral of Entity cnta is up to date.
Compiling vhdl file e:/vhdl/dianzheng/cont.vhdl in Library work.
Architecture behavioral of Entity cont is up to date.
Compiling vhdl file e:/vhdl/dianzheng/fpq10ms.vhdl in Library work.
Architecture behavioral of Entity fpq10ms is up to date.
Compiling vhdl file e:/vhdl/dianzheng/dianzheng.vhf in Library work.
Entity <dianzheng> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <dianzheng> (Architecture <BEHAVIORAL>).
Entity <dianzheng> analyzed. Unit <dianzheng> generated.

Analyzing Entity <chw> (Architecture <behavioral>).
Entity <chw> analyzed. Unit <chw> generated.

Analyzing Entity <cnta> (Architecture <behavioral>).
Entity <cnta> analyzed. Unit <cnta> generated.

Analyzing Entity <cont> (Architecture <behavioral>).
Entity <cont> analyzed. Unit <cont> generated.

Analyzing Entity <fpq10ms> (Architecture <behavioral>).
Entity <fpq10ms> analyzed. Unit <fpq10ms> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fpq10ms>.
    Related source file is e:/vhdl/dianzheng/fpq10ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 17-bit comparator lessequal for signal <$n0002>.
    Found 17-bit comparator greatequal for signal <$n0007>.
    Found 17-bit comparator lessequal for signal <$n0008>.
    Found 17-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq10ms> synthesized.


Synthesizing Unit <cont>.
    Related source file is e:/vhdl/dianzheng/cont.vhdl.
    Found 8-bit 4-to-1 multiplexer for signal <q>.
    Summary:
	inferred   8 Multiplexer(s).
Unit <cont> synthesized.


Synthesizing Unit <cnta>.
    Related source file is e:/vhdl/dianzheng/cnta.vhdl.
    Found 3-bit subtractor for signal <q>.
    Found 3-bit up counter for signal <tmp>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 Adder/Subtracter(s).
Unit <cnta> synthesized.


Synthesizing Unit <chw>.
    Related source file is e:/vhdl/dianzheng/chw.vhdl.
    Found 32-bit comparator less for signal <$n0002> created at line 24.
    Found 32-bit up counter for signal <cnt>.
    Found 2-bit up counter for signal <tmp>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 Comparator(s).
Unit <chw> synthesized.


Synthesizing Unit <dianzheng>.
    Related source file is e:/vhdl/dianzheng/dianzheng.vhf.
Unit <dianzheng> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 3-bit subtractor                  : 1
# Counters                         : 4
 32-bit up counter                 : 1
 17-bit up counter                 : 1
 2-bit up counter                  : 1
 3-bit up counter                  : 1
# Registers                        : 2
 1-bit register                    : 2
# Comparators                      : 4
 32-bit comparator less            : 1
 17-bit comparator lessequal       : 2
 17-bit comparator greatequal      : 1
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Tristates                        : 1
 1-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <dianzheng> ...

Optimizing unit <cont> ...

Optimizing unit <fpq10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dianzheng, actual ratio is 10.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      95  out of    768    12%  
 Number of Slice Flip Flops:            56  out of   1536     3%  
 Number of 4 input LUTs:               138  out of   1536     8%  
 Number of bonded IOBs:                 11  out of     96    11%  
 Number of TBUFs:                        1  out of    768     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================