lie_scan.vhdl

8*8点阵的实现

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;


entity dz_scan is
    port (clk: in STD_LOGIC;
          lie: out STD_LOGIC_VECTOR (7 downto 0);
          sel: in STD_LOGIC_VECTOR (2 downto 0));
end dz_scan;


architecture dz_scan_arch of dz_scan is
begin
process(clk)
begin 
  if (clk'event and clk='1' ) then
           case sel is
           when "000"=>lie<="10000000";
           when "001"=>lie<="01000000";
           when "010"=>lie<="00100000";
           when "011"=>lie<="00010000";
           when "100"=>lie<="00001000";
           when "101"=>lie<="00000100";
           when "110"=>lie<="00000010";
           when "111"=>lie<="00000001";
           when others=>lie<="00000000";
           end case;
   end if;
   end process;
  end dz_scan_arch;