clock.tan.rpt

来自「VHDL实现数字时钟」· RPT 代码 · 共 382 行 · 第 1/5 页

Timing Analyzer report for clock
Sat Feb 18 10:48:25 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                  ;
+------------------------------+-------+---------------+----------------------------------+---------------------+-------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                ; To                ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+---------------------+-------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; -1.029 ns                        ; rst                 ; fen1:inst|qout    ;            ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 18.358 ns                        ; sel:inst5|qout[0]   ; seg[6]            ; clk        ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; 9.185 ns                         ; rst                 ; fen60:inst7|carry ;            ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 76.27 MHz ( period = 13.111 ns ) ; fen24:inst4|tem1[3] ; sel:inst5|qout[3] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                     ;                   ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+---------------------+-------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM1270T144C5      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+