📄 clock.fit.rpt
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+--------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+---------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+---------------------+
; C4s ; 110 / 2,870 ( 3 % ) ;
; Direct links ; 50 / 3,938 ( 1 % ) ;
; Global clocks ; 4 / 4 ( 100 % ) ;
; LAB clocks ; 16 / 72 ( 22 % ) ;
; LUT chains ; 13 / 1,143 ( 1 % ) ;
; Local interconnects ; 227 / 3,938 ( 5 % ) ;
; R4s ; 83 / 2,832 ( 2 % ) ;
+----------------------------+---------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 6.88) ; Number of LABs (Total = 25) ;
+--------------------------------------------+------------------------------+
; 1 ; 3 ;
; 2 ; 1 ;
; 3 ; 2 ;
; 4 ; 0 ;
; 5 ; 2 ;
; 6 ; 3 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 1 ;
; 10 ; 10 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.96) ; Number of LABs (Total = 25) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 20 ;
; 1 Clock ; 18 ;
; 1 Clock enable ; 6 ;
; 1 Sync. load ; 1 ;
; 2 Clocks ; 4 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 7.20) ; Number of LABs (Total = 25) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 3 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 3 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 2 ;
; 10 ; 5 ;
; 11 ; 3 ;
; 12 ; 1 ;
; 13 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 5.80) ; Number of LABs (Total = 25) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 3 ;
; 2 ; 2 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 4 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 4 ;
; 9 ; 3 ;
; 10 ; 3 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 8.96) ; Number of LABs (Total = 25) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 3 ;
; 4 ; 5 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 3 ;
; 10 ; 2 ;
; 11 ; 3 ;
; 12 ; 2 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
; 17 ; 0 ;
; 18 ; 0 ;
; 19 ; 1 ;
; 20 ; 1 ;
; 21 ; 1 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sat Feb 18 10:46:46 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off clock -c clock
Info: Selected device EPM1270T144C5 for design "clock"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: Device EPM1270T144C5ES is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock
Info: Pin "clk" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted signal "fen100:inst2|qout" to use Global clock
Info: Automatically promoted signal "fen1:inst|qout" to use Global clock
Info: Automatically promoted signal "fen60:inst3|carry" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 6.081 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y9; Fanout = 7; REG Node = 'sel:inst5|qout[0]'
Info: 2: + IC(0.446 ns) + CELL(0.914 ns) = 1.360 ns; Loc. = LAB_X13_Y9; Fanout = 1; COMB Node = 'decode47:inst6|qout[7]~111'
Info: 3: + IC(2.399 ns) + CELL(2.322 ns) = 6.081 ns; Loc. = PIN_109; Fanout = 0; PIN Node = 'seg[7]'
Info: Total cell delay = 3.236 ns ( 53.21 % )
Info: Total interconnect delay = 2.845 ns ( 46.79 % )
Info: Fitter placement operations ending: elapsed time is 00:00:11
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 6%.
Info: Fitter routing operations ending: elapsed time is 00:00:03
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Feb 18 10:47:36 2006
Info: Elapsed time: 00:00:54
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