clock.map.summary

来自「VHDL实现数字时钟」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Wed Nov 23 14:26:38 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : MAX7000S
Device : EPM7128SLC84-15
Timing Models : Final
Met timing requirements : N/A
Total macrocells : 69
Total pins : 18