clock.tan.summary

来自「VHDL实现数字时钟」· SUMMARY 代码 · 共 47 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 17.000 ns
From           : data4[2]
To             : dataout[6]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 14.71 MHz ( period = 68.000 ns )
From           : h2_cnt[0]
To             : data4[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : h1_cnt[0]
To             : h2_cnt[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 8

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 8

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