📄 clock.map.rpt
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Analysis & Synthesis report for clock
Tue May 01 18:52:04 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Failed - Tue May 01 18:52:04 2007 ;
; Quartus II Version ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name ; clock ;
; Top-level Entity Name ; clock ;
; Family ; Cyclone ;
+-----------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP1C3T100C6 ; ;
; Top-level entity name ; clock ; clock ;
; Family name ; Cyclone ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M512 Memory Blocks ; Unlimited ; Unlimited ;
; Maximum Number of M4K Memory Blocks ; Unlimited ; Unlimited ;
; Maximum Number of M-RAM Memory Blocks ; Unlimited ; Unlimited ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
+--------------------------------------------------------------------+--------------------+--------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------+
; clock.bdf ; yes ; User Block Diagram/Schematic File ; E:/CPLDprogram/综合实验/数字时钟/clock.bdf ;
; decode47.vhd ; yes ; User VHDL File ; E:/CPLDprogram/综合实验/数字时钟/decode47.vhd ;
; sel.vhd ; yes ; User VHDL File ; E:/CPLDprogram/综合实验/数字时钟/sel.vhd ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue May 01 18:52:03 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 1 design units, including 1 entities, in source file clock.bdf
Info: Found entity 1: clock
Info: Found 2 design units, including 1 entities, in source file decode47.vhd
Info: Found design unit 1: decode47-behave
Info: Found entity 1: decode47
Info: Found 2 design units, including 1 entities, in source file sel.vhd
Info: Found design unit 1: sel-behave
Info: Found entity 1: sel
Info: Found 2 design units, including 1 entities, in source file fen60.vhd
Info: Found design unit 1: fen60-behave
Info: Found entity 1: fen60
Info: Found 2 design units, including 1 entities, in source file fen24.vhd
Info: Found design unit 1: fen24-behave
Info: Found entity 1: fen24
Info: Found 2 design units, including 1 entities, in source file fen1.vhd
Info: Found design unit 1: fen1-behave
Info: Found entity 1: fen1
Info: Found 2 design units, including 1 entities, in source file fen100.vhd
Info: Found design unit 1: fen100-behave
Info: Found entity 1: fen100
Info: Elaborating entity "clock" for the top level hierarchy
Info: Elaborating entity "decode47" for hierarchy "decode47:inst6"
Info: Elaborating entity "sel" for hierarchy "sel:inst5"
Error (10528): VHDL Signal or Variable Assignment Statement error at sel.vhd(63): value assigned to signal or variable must belong to signal or variable range File: E:/CPLDprogram/综合实验/数字时钟/sel.vhd Line: 63
Error (10528): VHDL Signal or Variable Assignment Statement error at sel.vhd(65): value assigned to signal or variable must belong to signal or variable range File: E:/CPLDprogram/综合实验/数字时钟/sel.vhd Line: 65
Error: Can't elaborate user hierarchy "sel:inst5"
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
Error: Processing ended: Tue May 01 18:52:04 2007
Error: Elapsed time: 00:00:01
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