📄 hdllint.lst

📁 麻省理工的一个实验室实现的MIPS IP CORE
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   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0x10d800):  
too many clock signals for reg "mem"

   clka_int (line 266)
   clkb_int (line 318)

if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on
上一页 1 2 3 45
💿 文件大小 28 K
👤 上传用户 sjb545893912
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#MIPS #CORE #IP #麻省理工
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