📄 hdllint.lst
字号:
[ on line #288 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #289 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #290 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #291 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #292 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #296 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #297 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #298 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #299 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #300 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #301 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #302 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #303 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #307 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #308 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #309 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #310 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #311 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #312 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #313 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
Verilog NOTE (0x4d00):
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #314 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: always reg
LINT CATEGORIES: verilog
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
LINT CATEGORIES: block
warning: Verilog WARNING (0x10d800):
too many clock signals for reg "mem"
clka_int (line 266)
clkb_int (line 318)
if "mem" isn't meant to be a flip-flop (for synthesis) you can
ignore this message
[ on line #318 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS: clock event_control event_stmt
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -