hdllint.lst

麻省理工的一个实验室实现的MIPS IP CORE

LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
doa_out1 is an implicit net in module RAMB4_S8_S8
[ on line #90 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
doa_out2 is an implicit net in module RAMB4_S8_S8
[ on line #91 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
doa_out3 is an implicit net in module RAMB4_S8_S8
[ on line #92 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
doa_out4 is an implicit net in module RAMB4_S8_S8
[ on line #93 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
doa_out5 is an implicit net in module RAMB4_S8_S8
[ on line #94 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
doa_out6 is an implicit net in module RAMB4_S8_S8
[ on line #95 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
doa_out7 is an implicit net in module RAMB4_S8_S8
[ on line #96 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
dob_out0 is an implicit net in module RAMB4_S8_S8
[ on line #98 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
dob_out1 is an implicit net in module RAMB4_S8_S8
[ on line #99 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
dob_out2 is an implicit net in module RAMB4_S8_S8
[ on line #100 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
dob_out3 is an implicit net in module RAMB4_S8_S8
[ on line #101 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
dob_out4 is an implicit net in module RAMB4_S8_S8
[ on line #102 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
dob_out5 is an implicit net in module RAMB4_S8_S8
[ on line #103 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
dob_out6 is an implicit net in module RAMB4_S8_S8
[ on line #104 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
dob_out7 is an implicit net in module RAMB4_S8_S8
[ on line #105 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x10d800):  
too many clock signals specified in event list:

   recovery_a (line 193)
   recovery_b (line 193)

[ on line #193 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0xdb00):  
there are at least 2 edges in an event statement; synthesis may
require only 1 of those edges
[ on line #193 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  event negedge posedge stmt synthesis
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x10d800):  
too many clock signals specified in event list:

   recovery_a (line 206)
   recovery_b (line 206)

[ on line #206 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0xdb00):  
there are at least 2 edges in an event statement; synthesis may
require only 1 of those edges
[ on line #206 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  event negedge posedge stmt synthesis
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x10d800):  
too many clock signals specified in event list:

   recovery_a (line 217)
   recovery_b (line 217)

[ on line #217 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  clock event_control event_stmt
LINT CATEGORIES:  block


warning:  Verilog WARNING (0xdb00):  
there are at least 2 edges in an event statement; synthesis may
require only 1 of those edges
[ on line #217 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  event negedge posedge stmt synthesis
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #233 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #234 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #235 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #236 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #237 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #238 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #239 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #240 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #244 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #245 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #246 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #247 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #248 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #249 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #250 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #251 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #255 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #256 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #257 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #258 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #259 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #260 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #261 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "doa_out" in different always blocks;
prior assignment at line 211
[ on line #262 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "mem" in different always blocks; prior
assignment at line 198
[ on line #269 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "mem" in different always blocks; prior
assignment at line 198
[ on line #270 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "mem" in different always blocks; prior
assignment at line 198
[ on line #271 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "mem" in different always blocks; prior
assignment at line 198
[ on line #272 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "mem" in different always blocks; prior
assignment at line 198
[ on line #273 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "mem" in different always blocks; prior
assignment at line 198
[ on line #274 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "mem" in different always blocks; prior
assignment at line 198
[ on line #275 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "mem" in different always blocks; prior
assignment at line 198
[ on line #276 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #285 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #286 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222
[ on line #287 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  always reg
LINT CATEGORIES:  verilog


Verilog NOTE (0x4d00):  
found assignments to reg "dob_out" in different always blocks;
prior assignment at line 222