hdllint.lst

麻省理工的一个实验室实现的MIPS IP CORE

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                        HDLLINT for Interactive Tool

                               Version 3.0.01


                                Produced by
                                -----------
           (c) Copyright 1996-1999, Everest Design Solutions, LLC
                            All rights reserved
           Sublicensed by Veritools, Inc. to Veritools' customers


option:  -y .
option:  -y e:/fndtn/verilog/src/UNIVIRTEX
   Reading VERILOG ... 
   reading PEMIPS.v ...
   scanning Verilog directory . ...
   found compiler directive "full_case" in comment starting on line 150 (file .\IF.v)
   found compiler directive "parallel_case" in comment starting on line 150 (file .\IF.v)
Verilog NOTE (0x2700):  
 changing size of constant from 4 to 5; extending bit value of
'1' to accommodate the change
[ on line #169 in file .\IF.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x5080):  
expression (size 33) is being assigned to an lval (size 32);
a bit may be dropped
[ on line #169 in file .\IF.v ]
LINT KEYWORDS:  assign expr lval
LINT CATEGORIES:  verilog


Verilog NOTE (0x2700):  
 changing size of constant from 3 to 4; extending bit value of
'1' to accommodate the change
[ on line #108 in file .\IF.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
bit 0 of reg LinkPC in module IF will be synthesized into a flip-flop
that doesn't have an asynchronous set or reset signal
[ in file .\IF.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg PCP8 in module IF will be synthesized
into a flip-flop that doesn't have an asynchronous set or reset
signal
[ in file .\IF.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 4-0 of reg LinkPCAddr in module IF will be synthesized
into a flip-flop that doesn't have an asynchronous set or reset
signal
[ in file .\IF.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg pc in module IF will be synthesized
into a flip-flop that doesn't have an asynchronous set or reset
signal
[ in file .\IF.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg i in module IF will be synthesized into
a flip-flop that doesn't have an asynchronous set or reset signal
[ in file .\IF.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


   scanning Verilog directory . ...
Verilog NOTE (0x12500):  
reading from output port "IRF2ALUUnlatched"
[ on line #86 in file .\RegFile.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


   scanning Verilog directory . ...
   scanning Verilog directory . ...
   scanning Verilog directory e:/fndtn/verilog/src/UNIVIRTEX ...
Verilog NOTE (0x209500):  
initial statement will be ignored during synthesis
[ on line #49 in file e:/fndtn/verilog/src/UNIVIRTEX\RAM16X1D.v ]
LINT KEYWORDS:  initial stmt synthesis
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
spo_int is an implicit net in module RAM16X1D
[ on line #43 in file e:/fndtn/verilog/src/UNIVIRTEX\RAM16X1D.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
dpo_int is an implicit net in module RAM16X1D
[ on line #44 in file e:/fndtn/verilog/src/UNIVIRTEX\RAM16X1D.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x315000):  
reg "count" not assigned any values in module "RAM16X1D"
[ on line #24 in file e:/fndtn/verilog/src/UNIVIRTEX\RAM16X1D.v ]
LINT KEYWORDS:  reg
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x9c00):  
inexact number of arguments specified in an instance; submod
"RAM32X32D" has 8 ports and therefore the instance should ideally
have 8 expressions (currently has 7 expressions); unconnected
ports:  WpData
[ on line #142 in file .\RegFile.v ]
LINT KEYWORDS:  expr instance module submodule
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg IRF2ALU in module RegFile will be synthesized
into a flip-flop that doesn't have an asynchronous set or reset
signal
[ in file .\RegFile.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg RaDataOut in module RegFile will be
synthesized into a flip-flop that doesn't have an asynchronous
set or reset signal
[ in file .\RegFile.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg RbDataOut in module RegFile will be
synthesized into a flip-flop that doesn't have an asynchronous
set or reset signal
[ in file .\RegFile.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
bit 0 of reg LinkPCRFOut in module RegFile will be synthesized
into a flip-flop that doesn't have an asynchronous set or reset
signal
[ in file .\RegFile.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 4-0 of reg LinkPCAddrRFOut in module RegFile will
be synthesized into a flip-flop that doesn't have an asynchronous
set or reset signal
[ in file .\RegFile.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 4-0 of reg raAddr0 in module RegFile will be synthesized
into a flip-flop that doesn't have an asynchronous set or reset
signal
[ in file .\RegFile.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 4-0 of reg raAddr1 in module RegFile will be synthesized
into a flip-flop that doesn't have an asynchronous set or reset
signal
[ in file .\RegFile.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 4-0 of reg rbAddr0 in module RegFile will be synthesized
into a flip-flop that doesn't have an asynchronous set or reset
signal
[ in file .\RegFile.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 4-0 of reg rbAddr1 in module RegFile will be synthesized
into a flip-flop that doesn't have an asynchronous set or reset
signal
[ in file .\RegFile.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


   scanning Verilog directory . ...
   found compiler directive "full_case" in comment starting on line 178 (file .\ALU.v)
   found compiler directive "parallel_case" in comment starting on line 178 (file .\ALU.v)
   found compiler directive "full_case" in comment starting on line 194 (file .\ALU.v)
   found compiler directive "parallel_case" in comment starting on line 194 (file .\ALU.v)
   found compiler directive "full_case" in comment starting on line 219 (file .\ALU.v)
   found compiler directive "parallel_case" in comment starting on line 219 (file .\ALU.v)
   found compiler directive "full_case" in comment starting on line 240 (file .\ALU.v)
   found compiler directive "parallel_case" in comment starting on line 240 (file .\ALU.v)
   found compiler directive "full_case" in comment starting on line 260 (file .\ALU.v)
   found compiler directive "parallel_case" in comment starting on line 260 (file .\ALU.v)
warning:  Verilog WARNING (0xe1c0):  
no default clause for case stmt
[ on line #240 in file .\ALU.v ]
LINT KEYWORDS:  case case_default stmt
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0xe1c0):  
no default clause for case stmt
[ on line #260 in file .\ALU.v ]
LINT KEYWORDS:  case case_default stmt
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x5080):  
expression (size 33) is being assigned to an lval (size 32);
a bit may be dropped
[ on line #213 in file .\ALU.v ]
LINT KEYWORDS:  assign expr lval
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg IALU2MEM in module ALU will be synthesized
into a flip-flop that doesn't have an asynchronous set or reset
signal
[ in file .\ALU.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg ALUResult in module ALU will be synthesized
into a flip-flop that doesn't have an asynchronous set or reset
signal
[ in file .\ALU.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 4-0 of reg ALUResultRegAddr in module ALU will be
synthesized into a flip-flop that doesn't have an asynchronous
set or reset signal
[ in file .\ALU.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg ALURtDataOut in module ALU will be synthesized
into a flip-flop that doesn't have an asynchronous set or reset
signal
[ in file .\ALU.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x12d80):  
synthesis will infer a latch for bits 31-0 of reg newALUResult
in module "ALU"
[ in file .\ALU.v ]
LINT KEYWORDS:  reg synthesis
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg newALUResult in module ALU will be synthesized
into a latch that doesn't have an asynchronous set or reset signal
[ in file .\ALU.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x12d80):  
synthesis will infer a latch for bits 31-0 of reg addResult in
module "ALU"
[ in file .\ALU.v ]
LINT KEYWORDS:  reg synthesis
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg addResult in module ALU will be synthesized
into a latch that doesn't have an asynchronous set or reset signal
[ in file .\ALU.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x12d80):  
synthesis will infer a latch for bits 31-0 of reg logResult in
module "ALU"
[ in file .\ALU.v ]
LINT KEYWORDS:  reg synthesis
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg logResult in module ALU will be synthesized
into a latch that doesn't have an asynchronous set or reset signal
[ in file .\ALU.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x12d80):  
synthesis will infer a latch for bits 31-0 of reg shiftResult
in module "ALU"
[ in file .\ALU.v ]
LINT KEYWORDS:  reg synthesis
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg shiftResult in module ALU will be synthesized
into a latch that doesn't have an asynchronous set or reset signal
[ in file .\ALU.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


Verilog NOTE (0x12d80):  
synthesis will infer a latch for bits 31-0 of reg setResult in
module "ALU"
[ in file .\ALU.v ]
LINT KEYWORDS:  reg synthesis
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg setResult in module ALU will be synthesized
into a latch that doesn't have an asynchronous set or reset signal
[ in file .\ALU.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


   scanning Verilog directory . ...
warning:  Verilog WARNING (0x13000):  
couldn't find signal "ALUResult" in the event list for an event
statement; you are recommended to add it to the event list; otherwise
you may have differing simulation results before and after synthesis
(e.g.  always @(ALUResult ... ) ... )
[ on line #72 in file .\MemStage.v ]
LINT KEYWORDS:  event_stmt sensitivity synthesis
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x5080):  
expression (size 32) is being assigned to an lval (size 9); some
bits may be dropped
[ on line #61 in file .\MemStage.v ]
LINT KEYWORDS:  assign expr lval
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x315000):  
reg "MemResultUnlatched" not assigned any values in module "MemStage"
[ on line #41 in file .\MemStage.v ]
LINT KEYWORDS:  reg
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x315000):  
reg "MemResultRegAddrUnlatched" not assigned any values in module
"MemStage"
[ on line #42 in file .\MemStage.v ]
LINT KEYWORDS:  reg
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 31-0 of reg MemResult in module MemStage will be
synthesized into a flip-flop that doesn't have an asynchronous
set or reset signal
[ in file .\MemStage.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
each of bits 4-0 of reg MemResultRegAddr in module MemStage will
be synthesized into a flip-flop that doesn't have an asynchronous
set or reset signal
[ in file .\MemStage.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


warning:  Verilog WARNING (0x12f00):  
bit 0 of reg MemResultValid in module MemStage will be synthesized
into a flip-flop that doesn't have an asynchronous set or reset
signal
[ in file .\MemStage.v ]
LINT KEYWORDS:  verilog
LINT CATEGORIES:  verilog


   scanning Verilog directory . ...
   scanning Verilog directory e:/fndtn/verilog/src/UNIVIRTEX ...
Verilog NOTE (0x209500):  
initial statement will be ignored during synthesis
[ on line #168 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  initial stmt synthesis
LINT CATEGORIES:  verilog


Verilog NOTE (0x8800):  
doa_out0 is an implicit net in module RAMB4_S8_S8
[ on line #89 in file e:/fndtn/verilog/src/UNIVIRTEX\RAMB4_S8_S8.v ]
LINT KEYWORDS:  verilog