mipstester000.v

麻省理工的一个实验室实现的MIPS IP CORE

/*
 Daniel L. Rosenband
 10/12/99
 
 MIPS Test
 
*/

module MIPSTester000 ();

   wire [31:0] ladUserOutData;
   
   reg kClk;
   reg mClk;
   wire mClk180;
   reg reset;
   reg [21:0] ladUserInAddr;
   reg [31:0] ladUserInData;
   reg 	      ladUserInRegStrobe_n;
   reg 	      ladUserInMemStrobe_n;
   reg 	      ladUserInWriteSel_n;

	reg [31:0] cycleCount;

   reg [31:0] tmp;
   
   always #15 kClk = !kClk;
   always #5 mClk = !mClk;
   assign     mClk180 = !mClk;

   initial
     begin
//	$dumpfile("vlog.dmp");
//	$dumpvars(0, MIPSTester000);

	cycleCount = 32'b0;

	kClk = 1'b1;
	mClk = 1'b1;
	reset = 1'b0;
	#15;
	reset = 1'b1;
	ladUserInAddr = 22'b0;
	ladUserInData = 32'b0;
	ladUserInRegStrobe_n = 1'b1;
	ladUserInMemStrobe_n = 1'b1;
	ladUserInWriteSel_n = 1'b1;
	#120;
	reset = 1'b0;
	WillLoadNewProg;
	#60;
	WritePEIMEM(9'h000, 32'hcafebabe);
	ClearPEIMEM;
	SetInitPEInstr;
	ReadPEIMEM(9'h000, tmp);
//	$display("ReadIMEM = 0x%x.", tmp);
	LoadedNewProg;
       $display("PC = 0x%x.", PEMIPS.IF.pc);
	#2400000;
       $display($time, "PC = 0x%x.", PEMIPS.IF.pc);
	$display("CycleCount = %d.", cycleCount);
	PrintStack(20);
	$finish;
     end // initial begin

   task SetInitPEInstr;
      begin
/*
       0x   0:  00 00 00 00    nop
       0x   4:  24 1d 07 ff    li $sp,2047
       0x   8:  0c 00 00 06    jal 6  { .text }
       0x   c:  00 00 00 00    nop
       0x  10:  08 00 00 04    j 4
       0x  14:  00 00 00 00    nop
       0x  18:  03 e0 00 08    jr $31
       0x  1c:  00 00 00 00    nop
*/	 
/*
main:
[   3] 0x   0:  27 bd ff f0    addiu $sp,$sp,-16
[   9] 0x   4:  24 0e 00 01    li $14,1
[  10] 0x   8:  24 0f 00 01    li $15,1
[   9] 0x   c:  af ae 00 0c    sw $14,12($sp)
[  10] 0x  10:  af af 00 08    sw $15,8($sp)
[  11] 0x  14:  af a0 00 00    sw $0,0($sp)
[  12] 0x  18:  8f b8 00 08    lw $24,8($sp)
[  11] 0x  1c:  8f aa 00 00    lw $10,0($sp)
[  13] 0x  20:  8f b9 00 0c    lw $25,12($sp)
[  12] 0x  24:  af b8 00 04    sw $24,4($sp)
[  14] 0x  28:  8f a8 00 04    lw $8,4($sp)
[  11] 0x  2c:  25 4b 00 01    addiu $11,$10,1
[  11] 0x  30:  29 61 00 0a    slti $1,$11,10
[  14] 0x  34:  03 28 48 21    addu $9,$25,$8
[  11] 0x  38:  af ab 00 00    sw $11,0($sp)
[  14] 0x  3c:  af a9 00 0c    sw $9,12($sp)
[  11] 0x  40:  14 20 ff f5    bne $1,$0,0x18
[  13] 0x  44:  af b9 00 08    sw $25,8($sp)
[  18] 0x  48:  8f a2 00 0c    lw $2,12($sp)
[  18] 0x  4c:  03 e0 00 08    jr $31
[  18] 0x  50:  27 bd 00 10    addiu $sp,$sp,16
[  18] 0x  54:  00 00 00 00    nop
[  18] 0x  58:  00 00 00 00    nop
[  18] 0x  5c:  00 00 00 00    nop	 
*/
	 WritePEIMEM(0, 32'h00000000);
	 WritePEIMEM(1, 32'h241d07fc);
	 WritePEIMEM(2, 32'h0c000006);
	 WritePEIMEM(3, 32'h00000000);
	 WritePEIMEM(4, 32'h08000004);
	 WritePEIMEM(5, 32'h00000000);

	 WritePEIMEM(6, 32'h0);
	 WritePEIMEM(7, 32'h27bdfff0); //    addiu $sp,$sp,-16
	 WritePEIMEM(8, 32'h240e0001); //    li $14,1
	 WritePEIMEM(9, 32'h240f0001); //    li $15,1
	 WritePEIMEM(10, 32'hafae000c); //    sw $14,12($sp)
	 WritePEIMEM(11, 32'hafaf0008); //    sw $15,8($sp)
	 WritePEIMEM(12, 32'hafa00000); //    sw $0,0($sp)
	 WritePEIMEM(13, 32'h8fb80008); //    lw $24,8($sp)
	 WritePEIMEM(14, 32'h8faa0000); //    lw $10,0($sp)
	 WritePEIMEM(15, 32'h8fb9000c); //    lw $25,12($sp)
	 WritePEIMEM(16, 32'hafb80004); //    sw $24,4($sp)
	 WritePEIMEM(17, 32'h8fa80004); //    lw $8,4($sp)
	 WritePEIMEM(18, 32'h254b0001); //    addiu $11,$10,1
	 WritePEIMEM(19, 32'h29617fff); //    slti $1,$11, infinity
	 WritePEIMEM(20, 32'h03284821); //    addu $9,$25,$8
	 WritePEIMEM(21, 32'hafab0000); //    sw $11,0($sp)
	 WritePEIMEM(22, 32'hafa9000c); //    sw $9,12($sp)
	 WritePEIMEM(23, 32'h1420fff5); //    bne $1,$0,0x18
	 WritePEIMEM(24, 32'hafb90008); //    sw $25,8($sp)
	 WritePEIMEM(25, 32'h8fa2000c); //    lw $2,12($sp)


	 WritePEIMEM(26, 32'h00000000); //    nop
	 WritePEIMEM(27, 32'h0800001b); // j 27
/*
	 WritePEIMEM(26, 32'h03e00008); //    jr $31
	 WritePEIMEM(27, 32'h27bd0010); //    addiu $sp,$sp,16
*/
	 WritePEIMEM(28, 32'h00000000); //    nop
	 WritePEIMEM(29, 32'h00000000); //    nop
	 WritePEIMEM(30, 32'h00000000); //    nop	 
       end
   endtask // SetInitPEInstr
   
   task ClearPEIMEM;
      integer i;
      begin
	 for (i = 0; i < 512; i = i +1)
	   WritePEIMEM(i[8:0], 0);
      end
   endtask // ClearPEIMEM
      
   task WillLoadNewProg;
      begin
	WritePEReg(13'h0004, 32'bx);
      end
   endtask
	 
   task LoadedNewProg;
      begin
	 WritePEReg(13'h0005, 32'bx);
      end
   endtask // LoadNewProg
      
   task WritePEReg;
      input [12:0] RegAddr;
      input [31:0] Data;

      begin
	 ladUserInAddr = {4'b0, 3'b010, RegAddr, 2'b00};
	 ladUserInRegStrobe_n = 1'b0;
	 ladUserInWriteSel_n = 1'b0;
	 ladUserInData = Data;
	 #30;
	 ladUserInAddr = 0;
	 ladUserInRegStrobe_n = 1'b1;
	 ladUserInWriteSel_n = 1'b1;
      end
   endtask // WritePEReg

   task ReadPEReg;
      input [12:0] RegAddr;
      output [31:0] Data;

      begin
	 ladUserInAddr = {4'b0, 3'b010, RegAddr, 2'b00};
	 ladUserInRegStrobe_n = 1'b0;
	 #30;
	 ladUserInAddr = 0;
	 ladUserInRegStrobe_n = 1'b1;
	 Data = ladUserOutData;
      end
   endtask // WritePEReg

   task WritePEIMEM;
      input [8:0] Addr;
      input [31:0] Data;

      begin
	 WritePEReg({4'b0111, Addr}, Data);
      end
   endtask // WritePEIMEM

   task ReadPEIMEM;
      input [8:0] Addr;
      output [31:0] Data;
      
      begin
	 ReadPEReg({4'b0111, Addr}, Data);
      end
   endtask // ReadPEIMEM

   task ReadPEDMEM;
      input [8:0] Addr;
      output [31:0] Data;
      
      begin
	 ReadPEReg({4'b0110, Addr}, Data);
      end
   endtask // ReadPEIMEM
   
   task PrintStack;
      input [10:0] NumToPrint;
      integer i;
      reg [31:0] tmp;
      begin
	 for (i = 0; i < NumToPrint; i = i + 1)
	   begin
	      ReadPEDMEM(9'h1ff - i, tmp);
	      $display("stack[%d] = 0x%x.", i, tmp);
	   end // for (i = 0; i < NumToPRint; i = i + 1)
      end
   endtask // PrintStack
   
/*
   always @ (posedge PEMIPS.RegFile.Clk)
     if (PEMIPS.RegFile.writeEnable_a && (PEMIPS.RegFile.writeAddress != 0))
       $display("Reg[%d] = 0x%x.", PEMIPS.RegFile.writeAddress, PEMIPS.RegFile.rwData);

   always @ (posedge PEMIPS.RegFile.Clk)
     if (PEMIPS.IF.pc != 0)
       $display("PC = 0x%x.", PEMIPS.IF.pc);

   always @ (posedge PEMIPS.DMEM.MClk180)
     if (PEMIPS.DMEM.XWE)
       $display("DMEM[0x%x] = 0x%x.", PEMIPS.DMEM.XAddr, PEMIPS.DMEM.XDataIn);
 
*/
	always @ (posedge PEMIPS.RegFile.Clk)
		cycleCount <= cycleCount + 1;
	
   PEMIPS PEMIPS (
		  // Outputs
		  .LADUserOutData       (ladUserOutData[31:0]),
		  // Inputs
		  .KClk			(kClk),
		  .MClk			(mClk),
		  .MClk180		(mClk180),
		  .Reset                (reset),
		  .LADUserInAddr	(ladUserInAddr[21:0]),
		  .LADUserInData	(ladUserInData[31:0]),
		  .LADUserInRegStrobe_n	(ladUserInRegStrobe_n),
		  .LADUserInMemStrobe_n	(ladUserInMemStrobe_n),
		  .LADUserInWriteSel_n	(ladUserInWriteSel_n));

endmodule // MIPSTester000