regfiletester000.v

麻省理工的一个实验室实现的MIPS IP CORE

/* 
Daniel L. Rosenband
9/30/99
*/

module RegFileTester000 ();

   wire [31:0] raData;
   wire [31:0] rbData;
   wire [31:0] rdiagData;

   reg 	       clk;
   reg 	       clkEN;
   reg [31:0]  rwData;
   reg [4:0]   rwAddr;
   reg 	       rwEN;
   reg [4:0]   raAddr;
   reg [4:0]   rbAddr;
   reg 	       rdiagEN;
   reg [4:0]   rdiagAddr;

   always #5 clk = !clk;
      
   initial
     begin
	$dumpfile("vlog.dmp");
	$dumpvars(0, RegFileTester000);

	clk = 1'b1;
	#5;
	clkEN = 1'b0;
	rwData = 32'b0;
	rwAddr = 5'b0;
	rwEN = 1'b0;
	raAddr = 5'b0;
	rbAddr = 5'b0;
	rdiagEN = 1'b0;
	rdiagAddr = 5'b0;
	#100;
	clkEN = 1'b1;
	SetRegistersInc;
	PrintAndCheckRaRb(0, 5);
	AccessRegFile(32'hffffffff, 0, 1'b1, 5, 0);
	PrintAndCheckRaRb(5, 32'hffffffff);
	AccessRegFile(32'h00000000, 0, 1'b1, 15, 0);
	PrintAndCheckRaRb(15, 32'h00000000);
	DiagnoseReg(7);
	CheckDiag(7);
	#500;
	$finish;
     end // initial begin

   task DiagnoseReg;
      input [4:0] a;
      begin
	 rdiagEN = 1'b1;
	 rdiagAddr = a;
	 #10;
	 rdiagEN = 1'b0;
      end
   endtask // DiagnoseReg

         
   task PrintRaRb;
      begin
	 $display($time, "  Ra = 0x%x;  Rb = 0x%x", raData, rbData);
      end
   endtask // PrintRaRb

   
   task PrintAndCheckRaRb;
      input [31:0] Ra;
      input [31:0] Rb;
      begin
	 PrintRaRb;
	 CheckRaRb(Ra, Rb);
      end
   endtask // PrintAndCheckRaRb
   
   task CheckRaRb;
      input [31:0] Ra;
      input [31:0] Rb;
      begin
	 if ((Ra !== raData) || (Rb !== rbData))
	   $display ("ERRPR!!! Ra pr Rb are not what they should be.");
      end
   endtask // CheckRaRb

   task CheckDiag;
      input [31:0] Rd;
      begin
	 if (Rd !== rdiagData)
	   $display ("ERRPR!!! RdiagData is not what it should be.");
      end
   endtask // CheckRaRb
      
   task SetRegistersInc;
      reg [10:0] i;
      begin
	 for (i = 0; i < 32; i = i + 1)
	   AccessRegFile(i, i, 1'b1, 0, 5);
      end
   endtask // SetRegistersInc
   
   task AccessRegFile;
      input [31:0] RwData;
      input [4:0] RwAddr;
      input RwEN;
      input [4:0] RaAddr;
      input [4:0] RbAddr;
      begin
	 rwData = RwData;
	 rwAddr = RwAddr;
	 rwEN = RwEN;
	 raAddr = RaAddr;
	 rbAddr = RbAddr;
	 #10;
	 rwData = 32'bx;
	 rwEN = 1'b0;
      end
   endtask // AccessRegFile
         
   RegFile RegFile (
		    // Outputs
		    .RaData		(raData[31:0]),
		    .RbData		(rbData[31:0]),
		    .RdiagData		(rdiagData[31:0]),
		    // Inputs
		    .Clk		(clk),
		    .ClkEN		(clkEN),
		    .RwData		(rwData[31:0]),
		    .RwAddr		(rwAddr[4:0]),
		    .RwEN		(rwEN),
		    .RaAddr		(raAddr[4:0]),
		    .RbAddr		(rbAddr[4:0]),
		    .RdiagEN		(rdiagEN),
		    .RdiagAddr		(rdiagAddr[4:0]));

endmodule // RegFileTester000