ram32x1d.v

麻省理工的一个实验室实现的MIPS IP CORE

/* 
Daniel L. Rosenband
9/30/99
*/

// 32x1 dual ported ram (one port read/write, one port read or write

module RAM32X1D (/*AUTOARG*/
   // Outputs
   RData, WpData, 
   // Inputs
   Clk, WData, WAddr, WEN_L, WEN_H, RAddr
   );
   output RData;		// data from read port
   output WpData;		// data from write port
      
   input Clk;
      
   input       WData;		// write data
   input [4:0] WAddr;		// write addr
   input       WEN_L;		// write enable (bit 4 is low)
   input       WEN_H;		// write enable (bit 4 is high)
   
   input [4:0] RAddr;		// read addr

   wire        wpData_L;	// data from lower addresses
   wire        wpData_H;	// data from higher addresses
   wire        rData_L;
   wire        rData_H;

   assign      RData = RAddr[4] ? rData_H : rData_L;
   assign      WpData = WAddr[4] ? wpData_H : wpData_L;
   
   RAM16X1D RAM16X1D_L (
			// Outputs
			.DPO		(rData_L),
			.SPO		(wpData_L),
			// Inputs
			.A0		(WAddr[0]),
			.A1		(WAddr[1]),
			.A2		(WAddr[2]),
			.A3		(WAddr[3]),
			.D		(WData),
			.DPRA0		(RAddr[0]),
			.DPRA1		(RAddr[1]),
			.DPRA2		(RAddr[2]),
			.DPRA3		(RAddr[3]),
			.WCLK		(Clk),
			.WE		(WEN_L));

   RAM16X1D RAM16X1D_H (
			// Outputs
			.DPO		(rData_H),
			.SPO		(wpData_H),
			// Inputs
			.A0		(WAddr[0]),
			.A1		(WAddr[1]),
			.A2		(WAddr[2]),
			.A3		(WAddr[3]),
			.D		(WData),
			.DPRA0		(RAddr[0]),
			.DPRA1		(RAddr[1]),
			.DPRA2		(RAddr[2]),
			.DPRA3		(RAddr[3]),
			.WCLK		(Clk),
			.WE		(WEN_H));

endmodule // RAM32X1D