xzq.vhdl

自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的歌曲

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity xzq is
 port(d:in std_logic_vector(6 downto 0);
      z:in std_logic_vector(4 downto 0);
		clk:in std_logic;
		qq:out std_logic_vector(3 downto 0);
		wx:out std_logic_vector(2 downto 0));
end xzq;

architecture Behavioral of xzq is
 signal t1,t2,t3:std_logic_vector(3 downto 0);
 signal s:std_logic_vector(1 downto 0);
begin
 process(clk)
   begin
	 t1<=z(4 downto 2) & d(6);
	 t2<=z(1) & d(5 downto 3);
	 t3<=z(0) & d(2 downto 0);
	 if clk='1' and clk'event then
	     if s="10" then
		     s<="00";
		  else
			  s<=s+1;
		  end if;
		 case s is 
		   when "00"=>qq<=t1;wx<="011";
			when "01"=>qq<=t2;wx<="101";
			when "10"=>qq<=t3;wx<="110";
			when others=>null;
		  end case;
		end if;
	  end process;
end Behavioral;