coregen.log

来自「自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的」· LOG 代码 · 共 22 行

# Xilinx CORE Generator 6.2i
# User = dragonlee
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in F:\dragon\VHDL\myboard\ok\lzhu\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=F:\dragon\VHDL\myboard\ok\lzhu
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=F:\dragon\VHDL\myboard\ok\lzhu
SETPROJECT .
Set current Project to F:\dragon\VHDL\myboard\ok\lzhu
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 2694
XIPCPJSENDCORES spartan2