__projnav.log

自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的歌曲

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/fp4mhz.vhdl in Library work.
Entity <fp4mhz> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

WARNING:HDLParsers:3215 - Unit work/SONG is now defined in a different file: was
   F:/dragon/VHDL/lzhu/song.vhdl, now is F:/dragon/VHDL/myboard/lzhu/song.vhdl
WARNING:HDLParsers:3215 - Unit work/SONG/BEHAVIORAL is now defined in a
   different file: was F:/dragon/VHDL/lzhu/song.vhdl, now is
   F:/dragon/VHDL/myboard/lzhu/song.vhdl
Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/song.vhdl in Library work.
Entity <song> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

WARNING:HDLParsers:3215 - Unit work/XZQ is now defined in a different file: was
   F:/dragon/VHDL/lzhu/xzq.vhdl, now is F:/dragon/VHDL/myboard/lzhu/xzq.vhdl
WARNING:HDLParsers:3215 - Unit work/XZQ/BEHAVIORAL is now defined in a different
   file: was F:/dragon/VHDL/lzhu/xzq.vhdl, now is
   F:/dragon/VHDL/myboard/lzhu/xzq.vhdl
Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/xzq.vhdl in Library work.
Entity <xzq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 60
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/xzq.vhdl in Library work.
Architecture behavioral of Entity xzq is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <xzq> (Architecture <behavioral>).
WARNING:Xst:819 - F:/dragon/VHDL/myboard/lzhu/xzq.vhdl line 23: The following signals are missing in the process sensitivity list:
   z<3>, d, z.
Entity <xzq> analyzed. Unit <xzq> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <xzq>.
    Related source file is F:/dragon/VHDL/myboard/lzhu/xzq.vhdl.
    Found 4-bit register for signal <qq>.
    Found 3-bit register for signal <wx>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0002> created at line 34.
    Found 2-bit up counter for signal <s>.
    Summary:
	inferred   1 Counter(s).
	inferred   7 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <xzq> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 2-bit up counter                  : 1
# Registers                        : 2
 3-bit register                    : 1
 4-bit register                    : 1
# Multiplexers                     : 1
 4-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <xzq> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx6.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block xzq, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                       7  out of    768     0%  
 Number of Slice Flip Flops:             9  out of   1536     0%  
 Number of 4 input LUTs:                14  out of   1536     0%  
 Number of bonded IOBs:                 19  out of     96    19%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 9     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.653ns (Maximum Frequency: 176.897MHz)
   Minimum input arrival time before clock: 3.384ns
   Maximum output required time after clock: 6.959ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

WARNING:HDLParsers:3215 - Unit work/YMQ is now defined in a different file: was
   F:/dragon/VHDL/lzhu/ymq.vhdl, now is F:/dragon/VHDL/myboard/lzhu/ymq.vhdl
WARNING:HDLParsers:3215 - Unit work/YMQ/BEHAVIORAL is now defined in a different
   file: was F:/dragon/VHDL/lzhu/ymq.vhdl, now is
   F:/dragon/VHDL/myboard/lzhu/ymq.vhdl
Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/ymq.vhdl in Library work.
Entity <ymq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 60
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/LZ is now defined in a different file: was F:/dragon/VHDL/lzhu/lz.vhf, now is F:/dragon/VHDL/myboard/lzhu/lz.vhf
WARNING:HDLParsers:3215 - Unit work/LZ/BEHAVIORAL is now defined in a different file: was F:/dragon/VHDL/lzhu/lz.vhf, now is F:/dragon/VHDL/myboard/lzhu/lz.vhf
Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/fpq4hz.vhdl in Library work.
Architecture behavioral of Entity fpq4hz is up to date.
Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/song.vhdl in Library work.
Architecture behavioral of Entity song is up to date.
Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/ymq.vhdl in Library work.
Architecture behavioral of Entity ymq is up to date.
Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/xzq.vhdl in Library work.
Architecture behavioral of Entity xzq is up to date.
Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/fp01ms.vhdl in Library work.
Architecture behavioral of Entity fp01ms is up to date.
Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/fp4mhz.vhdl in Library work.
Architecture behavioral of Entity fp4mhz is up to date.
Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/lz.vhf in Library work.
Entity <lz> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <lz> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - F:/dragon/VHDL/myboard/lzhu/lz.vhf line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <lz> analyzed. Unit <lz> generated.

Analyzing Entity <fpq4hz> (Architecture <behavioral>).
Entity <fpq4hz> analyzed. Unit <fpq4hz> generated.

Analyzing Entity <song> (Architecture <behavioral>).
WARNING:Xst:819 - F:/dragon/VHDL/myboard/lzhu/song.vhdl line 48: The following signals are missing in the process sensitivity list:
   counter.
Entity <song> analyzed. Unit <song> generated.

Analyzing Entity <ymq> (Architecture <behavioral>).
Entity <ymq> analyzed. Unit <ymq> generated.

Analyzing Entity <xzq> (Architecture <behavioral>).
WARNING:Xst:819 - F:/dragon/VHDL/myboard/lzhu/xzq.vhdl line 23: The following signals are missing in the process sensitivity list:
   z<3>, d, z.
Entity <xzq> analyzed. Unit <xzq> generated.

Analyzing Entity <fp01ms> (Architecture <behavioral>).
Entity <fp01ms> analyzed. Unit <fp01ms> generated.

Analyzing Entity <fp4mhz> (Architecture <behavioral>).
Entity <fp4mhz> analyzed. Unit <fp4mhz> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fp4mhz>.
    Related source file is F:/dragon/VHDL/myboard/lzhu/fp4mhz.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 4-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   1 Tristate(s).
Unit <fp4mhz> synthesized.


Synthesizing Unit <fp01ms>.
    Related source file is F:/dragon/VHDL/myboard/lzhu/fp01ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 12-bit comparator lessequal for signal <$n0002>.
    Found 12-bit comparator greatequal for signal <$n0007>.
    Found 12-bit comparator lessequal for signal <$n0008>.
    Found 12-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fp01ms> synthesized.


Synthesizing Unit <xzq>.
    Related source file is F:/dragon/VHDL/myboard/lzhu/xzq.vhdl.
    Found 4-bit register for signal <qq>.
    Found 3-bit register for signal <wx>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0002> created at line 34.
    Found 2-bit up counter for signal <s>.
    Summary:
	inferred   1 Counter(s).
	inferred   7 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <xzq> synthesized.


Synthesizing Unit <ymq>.
    Related source file is F:/dragon/VHDL/myboard/lzhu/ymq.vhdl.
WARNING:Xst:737 - Found 7-bit latch for signal <Q>.
Unit <ymq> synthesized.


Synthesizing Unit <song>.
    Related source file is F:/dragon/VHDL/myboard/lzhu/song.vhdl.
    Found 256x7-bit ROM for signal <digit>.
    Found 1-bit register for signal <speaker>.
    Found 1-bit register for signal <carrier>.
    Found 2-bit up counter for signal <count>.
    Found 8-bit up counter for signal <counter>.
    Found 13-bit up counter for signal <divider>.
    Summary:
	inferred   1 ROM(s).
	inferred   3 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <song> synthesized.


Synthesizing Unit <fpq4hz>.
    Relat