__projnav.log

自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的歌曲

Design Summary:
Number of errors:      0
Number of warnings:    3
Logic Utilization:
  Number of Slice Flip Flops:        86 out of  1,536    5%
  Number of 4 input LUTs:           213 out of  1,536   13%
Logic Distribution:
    Number of occupied Slices:                         161 out of    768   20%
    Number of Slices containing only related logic:    161 out of    161  100%
    Number of Slices containing unrelated logic:         0 out of    161    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          277 out of  1,536   18%
      Number used as logic:                       213
      Number used as a route-thru:                 64
   Number of bonded IOBs:            11 out of     92   11%
      IOB Flip Flops:                               1
      IOB Latches:                                  7
   Number of Tbufs:                   2 out of    832    1%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  2,657
Additional JTAG gate count for IOBs:  576
Peak Memory Usage:  73 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "lz_map.mrp" for details.
Completed process "Map".

Mapping Module lz . . .
MAP command line:
map -intstyle ise -p xc2s50-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o lz_map.ncd lz.ngd lz.pcf
Mapping Module lz: DONE



Started process "Place & Route".





Constraints file: lz.pcf

Loading device database for application Par from file "lz_map.ncd".
   "lz" is an NCD, version 2.38, device xc2s50, package tq144, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            11 out of 92     11%
      Number of LOCed External IOBs   11 out of 11    100%

   Number of SLICEs                  161 out of 768    20%

   Number of GCLKs                     1 out of 4      25%
   Number of TBUFs                     2 out of 832     1%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989c91) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
..............................
Phase 5.8 (Checksum:9a8584) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file lz.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 965 unrouted;       REAL time: 2 secs 

Phase 2: 915 unrouted;       REAL time: 10 secs 

Phase 3: 231 unrouted;       REAL time: 10 secs 

Phase 4: 0 unrouted;       REAL time: 10 secs 

Total REAL time to Router completion: 11 secs 
Total CPU time to Router completion: 9 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   25   |  0.076     |  0.470      |
+----------------------------+----------+--------+------------+-------------+
|     XLXI_1_OUTCLK          |Low-Skew  |    9   |  0.430     |  4.354      |
+----------------------------+----------+--------+------------+-------------+
|            XLXN_2          |   Local  |    9   |  0.282     |  2.323      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_3_carrier          |   Local  |    3   |  1.409     |  2.647      |
+----------------------------+----------+--------+------------+-------------+
|            XLXN_8          |   Local  |    5   |  0.108     |  1.754      |
+----------------------------+----------+--------+------------+-------------+
|     XLXI_5__n0001          |   Local  |    7   |  0.300     |  2.760      |
+----------------------------+----------+--------+------------+-------------+
|        XLXI_1_CLK          |   Local  |    3   |  0.024     |  2.557      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 12 secs 
Total CPU time to PAR completion: 10 secs 

Peak Memory Usage:  65 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file lz.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Thu Mar 29 22:28:33 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module lz . . .
PAR command line: par -w -intstyle ise -ol std -t 1 lz_map.ncd lz.ncd lz.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/fp01ms.vhdl in Library work.
Entity <fp01ms> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

WARNING:HDLParsers:3215 - Unit work/FPQ4HZ is now defined in a different file:
   was F:/dragon/VHDL/lzhu/fpq4hz.vhdl, now is
   F:/dragon/VHDL/myboard/lzhu/fpq4hz.vhdl
WARNING:HDLParsers:3215 - Unit work/FPQ4HZ/BEHAVIORAL is now defined in a
   different file: was F:/dragon/VHDL/lzhu/fpq4hz.vhdl, now is
   F:/dragon/VHDL/myboard/lzhu/fpq4hz.vhdl
Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/fpq4hz.vhdl in Library work.
Entity <fpq4hz> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 60
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/dragon/VHDL/myboard/lzhu/fp4mhz.vhdl in Library work.
Entity <fp4mhz> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <fp4mhz> (Architecture <Behavioral>).
Entity <fp4mhz> analyzed. Unit <fp4mhz> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fp4mhz>.
    Related source file is F:/dragon/VHDL/myboard/lzhu/fp4mhz.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 4-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   1 Tristate(s).
Unit <fp4mhz> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 4-bit up counter                  : 1
# Registers                        : 2
 1-bit register                    : 2
# Tristates                        : 1
 1-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <fp4mhz> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx6.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fp4mhz, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                       5  out of    768     0%  
 Number of Slice Flip Flops:             6  out of   1536     0%  
 Number of 4 input LUTs:                 6  out of   1536     0%  
 Number of bonded IOBs:                  1  out of     96     1%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.248ns (Maximum Frequency: 190.549MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 6.927ns
   Maximum combinational path delay: No path found