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自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的歌曲

Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/dragon/VHDL/lzhu/fpq2_5.vhdl in Library work.
Architecture behavioral of Entity fpq2_5 is up to date.
Compiling vhdl file F:/dragon/VHDL/lzhu/fpq4hz.vhdl in Library work.
Architecture behavioral of Entity fpq4hz is up to date.
Compiling vhdl file F:/dragon/VHDL/lzhu/song.vhdl in Library work.
Architecture behavioral of Entity song is up to date.
Compiling vhdl file F:/dragon/VHDL/lzhu/fpq2ms.vhdl in Library work.
Architecture behavioral of Entity fpq2ms is up to date.
Compiling vhdl file F:/dragon/VHDL/lzhu/ymq.vhdl in Library work.
Architecture behavioral of Entity ymq is up to date.
Compiling vhdl file F:/dragon/VHDL/lzhu/xzq.vhdl in Library work.
Architecture behavioral of Entity xzq is up to date.
Compiling vhdl file F:/dragon/VHDL/lzhu/lz.vhf in Library work.
Entity <lz> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <lz> (Architecture <BEHAVIORAL>).
INFO:Xst:1739 - HDL ADVISOR - F:/dragon/VHDL/lzhu/lz.vhf line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - F:/dragon/VHDL/lzhu/lz.vhf line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <lz> analyzed. Unit <lz> generated.

Analyzing Entity <fpq2_5> (Architecture <behavioral>).
Entity <fpq2_5> analyzed. Unit <fpq2_5> generated.

Analyzing Entity <fpq4hz> (Architecture <behavioral>).
Entity <fpq4hz> analyzed. Unit <fpq4hz> generated.

Analyzing Entity <song> (Architecture <behavioral>).
WARNING:Xst:819 - F:/dragon/VHDL/lzhu/song.vhdl line 48: The following signals are missing in the process sensitivity list:
   counter.
Entity <song> analyzed. Unit <song> generated.

Analyzing Entity <fpq2ms> (Architecture <behavioral>).
Entity <fpq2ms> analyzed. Unit <fpq2ms> generated.

Analyzing Entity <ymq> (Architecture <behavioral>).
Entity <ymq> analyzed. Unit <ymq> generated.

Analyzing Entity <xzq> (Architecture <behavioral>).
WARNING:Xst:819 - F:/dragon/VHDL/lzhu/xzq.vhdl line 23: The following signals are missing in the process sensitivity list:
   z<3>, d, z.
Entity <xzq> analyzed. Unit <xzq> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <xzq>.
    Related source file is F:/dragon/VHDL/lzhu/xzq.vhdl.
    Found 4-bit register for signal <qq>.
    Found 3-bit register for signal <wx>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0002> created at line 34.
    Found 2-bit up counter for signal <s>.
    Summary:
	inferred   1 Counter(s).
	inferred   7 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <xzq> synthesized.


Synthesizing Unit <ymq>.
    Related source file is F:/dragon/VHDL/lzhu/ymq.vhdl.
WARNING:Xst:737 - Found 7-bit latch for signal <Q>.
Unit <ymq> synthesized.


Synthesizing Unit <fpq2ms>.
    Related source file is F:/dragon/VHDL/lzhu/fpq2ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 15-bit comparator lessequal for signal <$n0002>.
    Found 15-bit comparator greatequal for signal <$n0007>.
    Found 15-bit comparator lessequal for signal <$n0008>.
    Found 15-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq2ms> synthesized.


Synthesizing Unit <song>.
    Related source file is F:/dragon/VHDL/lzhu/song.vhdl.
    Found 256x7-bit ROM for signal <digit>.
    Found 1-bit register for signal <speaker>.
    Found 1-bit register for signal <carrier>.
    Found 2-bit up counter for signal <count>.
    Found 8-bit up counter for signal <counter>.
    Found 13-bit up counter for signal <divider>.
    Summary:
	inferred   1 ROM(s).
	inferred   3 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <song> synthesized.


Synthesizing Unit <fpq4hz>.
    Related source file is F:/dragon/VHDL/lzhu/fpq4hz.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 22-bit comparator lessequal for signal <$n0002>.
    Found 22-bit comparator greatequal for signal <$n0007>.
    Found 22-bit comparator lessequal for signal <$n0008>.
    Found 22-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq4hz> synthesized.


Synthesizing Unit <fpq2_5>.
    Related source file is F:/dragon/VHDL/lzhu/fpq2_5.vhdl.
WARNING:Xst:646 - Signal <clk1> is assigned but never used.
    Found 1-bit register for signal <OUTCLK>.
    Found 1-bit xor2 for signal <CLK>.
    Found 4-bit down counter for signal <COUNT>.
    Found 1-bit register for signal <divide2>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <fpq2_5> synthesized.


Synthesizing Unit <lz>.
    Related source file is F:/dragon/VHDL/lzhu/lz.vhf.
Unit <lz> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 256x7-bit ROM                     : 1
# Counters                         : 7
 13-bit up counter                 : 1
 22-bit up counter                 : 1
 8-bit up counter                  : 1
 15-bit up counter                 : 1
 4-bit down counter                : 1
 2-bit up counter                  : 2
# Registers                        : 10
 1-bit register                    : 8
 3-bit register                    : 1
 4-bit register                    : 1
# Latches                          : 1
 7-bit latch                       : 1
# Comparators                      : 6
 22-bit comparator lessequal       : 2
 22-bit comparator greatequal      : 1
 15-bit comparator lessequal       : 2
 15-bit comparator greatequal      : 1
# Multiplexers                     : 1
 4-bit 4-to-1 multiplexer          : 1
# Tristates                        : 2
 1-bit tristate buffer             : 2
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <wx_2> (without init value) is constant in block <xzq>.
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <lz> ...

Optimizing unit <fpq4hz> ...

Optimizing unit <fpq2ms> ...

Optimizing unit <ymq> ...

Optimizing unit <song> ...

Optimizing unit <xzq> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lz, actual ratio is 21.
FlipFlop XLXI_3_counter_3 has been replicated 1 time(s)
FlipFlop XLXI_3_counter_2 has been replicated 1 time(s)
FlipFlop XLXI_3_counter_1 has been replicated 1 time(s)
FlipFlop XLXI_3_counter_0 has been replicated 1 time(s)
FlipFlop XLXI_3_counter_4 has been replicated 1 time(s)
FlipFlop XLXI_3_counter_3 has been replicated 1 time(s)
FlipFlop XLXI_3_counter_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                     158  out of    768    20%  
 Number of Slice Flip Flops:            94  out of   1536     6%  
 Number of 4 input LUTs:               277  out of   1536    18%  
 Number of bonded IOBs:                 11  out of     96    11%  
 Number of TBUFs:                        2  out of    768     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_1_CLK(XLXI_1_Mxor_CLK_Result1:O)| NONE(*)(XLXI_1_OUTCLK) | 5     |
clk                                | BUFGP                  | 41    |
XLXI_1_OUTCLK:Q                    | NONE                   | 15    |
XLXI_5__n0001(XLXI_5__n00011:O)    | NONE(*)(XLXI_5_Q_2)    | 7     |
XLXI_3_carrier:Q                   | NONE                   | 3     |
XLXN_2(XLXI_2_I3_0:O)              | NONE(*)(XLXI_3_counter_4_1)| 15    |
XLXN_8(XLXI_4_I3_0:O)              | NONE(*)(XLXI_6_qq_1)   | 8     |
-----------------------------------+------------------------+-------+
(*) These 4 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.644ns (Maximum Frequency: 103.691MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 6.959ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
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Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd f:\dragon\vhdl\lzhu/_ngo -uc yj.ucf -p
xc2s50-tq144-6 lz.ngc lz.ngd 

Reading NGO file "F:/dragon/VHDL/lzhu/lz.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "yj.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:477 - clock net 'clk_BUFGP' has non-clock connections. These
   problematic connections include:
     pin I1 on block XLXI_1_Mxor_CLK_Result1 with type LUT2

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Total memory usage is 53040 kilobytes

Writing NGD file "lz.ngd" ...

Writing NGDBUILD log file "lz.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd f:\dragon\vhdl\lzhu/_ngo -uc yj.ucf -p
xc2s50-tq144-6 lz.ngc lz.ngd 

Reading NGO file "F:/dragon/VHDL/lzhu/lz.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "yj.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:477 - clock net 'clk_BUFGP' has non-clock connections. These
   problematic connections include:
     pin I1 on block XLXI_1_Mxor_CLK_Result1 with type LUT2

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Total memory usage is 54000 kilobytes

Writing NGD file "lz.ngd" ...

Writing NGDBUILD log file "lz.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50tq144-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...