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=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/dragon/VHDL/lzhu/fpq2_5.vhdl in Library work.ERROR:HDLParsers:1202 - F:/dragon/VHDL/lzhu/fpq2_5.vhdl Line 18. Redeclaration of symbol divide2.--> Total memory usage is 61576 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/dragon/VHDL/lzhu/fpq2_5.vhdl in Library work.Entity <FPQ2_5> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <fpq2_5> (Architecture <Behavioral>).INFO:Xst:1739 - HDL ADVISOR - F:/dragon/VHDL/lzhu/fpq2_5.vhdl line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.Entity <fpq2_5> analyzed. Unit <fpq2_5> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <fpq2_5>. Related source file is F:/dragon/VHDL/lzhu/fpq2_5.vhdl.WARNING:Xst:646 - Signal <clk1> is assigned but never used. Found 1-bit register for signal <OUTCLK>. Found 1-bit xor2 for signal <CLK>. Found 4-bit down counter for signal <COUNT>. Found 1-bit register for signal <divide2>. Summary: inferred 1 Counter(s). inferred 2 D-type flip-flop(s).Unit <fpq2_5> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 1 4-bit down counter : 1# Registers : 2 1-bit register : 2# Xors : 1 1-bit xor2 : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <fpq2_5> ...Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block fpq2_5, actual ratio is 0.FlipFlop OUTCLK has been replicated 1 time(s) to handle iob=true attribute.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-6 Number of Slices: 7 out of 768 0% Number of Slice Flip Flops: 7 out of 1536 0% Number of 4 input LUTs: 7 out of 1536 0% Number of bonded IOBs: 2 out of 96 2% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+CLK(Mxor_CLK_Result1:O) | NONE(*)(COUNT_3) | 6 |OUTCLK:Q | NONE | 1 |-----------------------------------+------------------------+-------+(*) This 1 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -6 Minimum period: 5.140ns (Maximum Frequency: 194.553MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 6.788ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file F:/dragon/VHDL/lzhu/fpq2_5.vhdl in Library work.Entity <fpq2_5> (Architecture <behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file F:/dragon/VHDL/lzhu/fpq2ms.vhdl in Library work.Entity <fpq2ms> (Architecture <Behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/dragon/VHDL/lzhu/xzq.vhdl in Library work.ERROR:HDLParsers:164 - F:/dragon/VHDL/lzhu/xzq.vhdl Line 15. parse error, unexpected COLON, expecting IDENTIFIER or STRING_LITERAL--> Total memory usage is 61704 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/dragon/VHDL/lzhu/xzq.vhdl in Library work.ERROR:HDLParsers:164 - F:/dragon/VHDL/lzhu/xzq.vhdl Line 15. parse error, unexpected COLON, expecting IDENTIFIER or STRING_LITERAL--> Total memory usage is 61704 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/dragon/VHDL/lzhu/xzq.vhdl in Library work.Entity <xzq> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <xzq> (Architecture <Behavioral>).WARNING:Xst:819 - F:/dragon/VHDL/lzhu/xzq.vhdl line 23: The following signals are missing in the process sensitivity list: z<3>, d, z.Entity <xzq> analyzed. Unit <xzq> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <xzq>. Related source file is F:/dragon/VHDL/lzhu/xzq.vhdl. Found 4-bit register for signal <qq>. Found 3-bit register for signal <wx>. Found 4-bit 4-to-1 multiplexer for signal <$n0002> created at line 34. Found 2-bit up counter for signal <s>. Summary: inferred 1 Counter(s). inferred 7 D-type flip-flop(s). inferred 4 Multiplexer(s).Unit <xzq> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 1 2-bit up counter : 1# Registers : 2 3-bit register : 1 4-bit register : 1# Multiplexers : 1 4-bit 4-to-1 multiplexer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1710 - FF/Latch <wx_2> (without init value) is constant in block <xzq>.Optimizing unit <xzq> ...Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block xzq, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-6 Number of Slices: 7 out of 768 0% Number of Slice Flip Flops: 8 out of 1536 0% Number of 4 input LUTs: 13 out of 1536 0% Number of bonded IOBs: 19 out of 96 19% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 8 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: 5.563ns (Maximum Frequency: 179.759MHz) Minimum input arrival time before clock: 3.384ns Maximum output required time after clock: 6.959ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file F:/dragon/VHDL/lzhu/xzq.vhdl in Library work.Entity <xzq> (Architecture <behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file F:/dragon/VHDL/lzhu/ymq.vhdl in Library work.Entity <YMQ> (Architecture <Behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
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