lz.par

自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的歌曲

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

DRAGONLEE::  Thu Apr 12 19:44:40 2007


C:/Xilinx6/bin/nt/par.exe -w -intstyle ise -ol std -t 1 lz_map.ncd lz.ncd
lz.pcf 


Constraints file: lz.pcf
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 60
   days, this program will not operate. For more information about thisproduct,
   please refer to the Evaluation Agreement, which was shipped toyou along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact yourlocal
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to:[e-mail]
   Thank You!

Loading device database for application Par from file "lz_map.ncd".
   "lz" is an NCD, version 2.38, device xc2s50, package tq144, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/Xilinx6.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolved that IOB <wx<0>> must be placed at site P23.
Resolved that IOB <wx<1>> must be placed at site P22.
Resolved that IOB <wx<2>> must be placed at site P13.
Resolved that IOB <q<0>> must be placed at site P140.
Resolved that IOB <q<1>> must be placed at site P139.
Resolved that IOB <q<2>> must be placed at site P141.
Resolved that IOB <q<3>> must be placed at site P4.
Resolved that IOB <q<4>> must be placed at site P5.
Resolved that IOB <q<5>> must be placed at site P6.
Resolved that IOB <q<6>> must be placed at site P7.
Resolved that IOB <sp> must be placed at site P103.
Resolved that GCLKIOB <clk> must be placed at site P18.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            11 out of 92     11%
      Number of LOCed External IOBs   11 out of 11    100%

   Number of SLICEs                  151 out of 768    19%

   Number of GCLKs                     1 out of 4      25%
   Number of TBUFs                     2 out of 832     1%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989bba) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
..........................
Phase 5.8 (Checksum:9d1ba0) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file lz.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 924 unrouted;       REAL time: 2 secs 

Phase 2: 878 unrouted;       REAL time: 9 secs 

Phase 3: 246 unrouted;       REAL time: 9 secs 

Phase 4: 0 unrouted;       REAL time: 9 secs 

Total REAL time to Router completion: 9 secs 
Total CPU time to Router completion: 7 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   30   |  0.087     |  0.465      |
+----------------------------+----------+--------+------------+-------------+
|     XLXI_5__n0001          |Low-Skew  |    7   |  1.175     |  4.001      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_3_carrier          |   Local  |    3   |  0.007     |  2.811      |
+----------------------------+----------+--------+------------+-------------+
|            XLXN_8          |   Local  |    6   |  0.499     |  2.364      |
+----------------------------+----------+--------+------------+-------------+
|            XLXN_2          |   Local  |    9   |  0.464     |  2.623      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 164


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.159
   The MAXIMUM PIN DELAY IS:                               4.001
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.424

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         409         424          86           4           1           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 10 secs 
Total CPU time to PAR completion: 8 secs 

Peak Memory Usage:  54 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file lz.ncd.


PAR done.