fp01ms.vhdl

来自「自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的」· VHDL 代码 · 共 35 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fp01ms is
      Port (CLK:in std_logic;
	       CP:out std_logic);
end fp01ms;

architecture Behavioral of fp01ms is
  signal a:integer range 0 to 4000;
    begin
		process(CLK)
		begin
		  if(CLK'event and CLK='1') then
		     if a=3999 then
			       a<=0;
				else
				  a<=a+1;
				end if;
			 case a is
			 when 0      to 1999=>CP<='1';
			 when 2000 to 3999=>CP<='0';
			 when others =>CP<='Z';
			 end case;
			end if;
		 end process;
end Behavioral;