fpq2_5.syr

自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的歌曲

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: fpq2_5.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : fpq2_5.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : fpq2_5
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : fpq2_5
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : fpq2_5.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/dragon/VHDL/lzhu/fpq2_5.vhdl in Library work.
Entity <FPQ2_5> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <fpq2_5> (Architecture <Behavioral>).
INFO:Xst:1739 - HDL ADVISOR - F:/dragon/VHDL/lzhu/fpq2_5.vhdl line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <fpq2_5> analyzed. Unit <fpq2_5> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fpq2_5>.
    Related source file is F:/dragon/VHDL/lzhu/fpq2_5.vhdl.
WARNING:Xst:646 - Signal <clk1> is assigned but never used.
    Found 1-bit register for signal <OUTCLK>.
    Found 1-bit xor2 for signal <CLK>.
    Found 4-bit down counter for signal <COUNT>.
    Found 1-bit register for signal <divide2>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <fpq2_5> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 4-bit down counter                : 1
# Registers                        : 2
 1-bit register                    : 2
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <fpq2_5> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fpq2_5, actual ratio is 0.
FlipFlop OUTCLK has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : fpq2_5.ngr
Top Level Output File Name         : fpq2_5
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 2

Macro Statistics :
# Registers                        : 6
#      1-bit register              : 6
# Adders/Subtractors               : 1
#      4-bit subtractor            : 1

Cell Usage :
# BELS                             : 16
#      GND                         : 1
#      LUT1_L                      : 4
#      LUT2                        : 1
#      LUT4                        : 2
#      MUXCY                       : 3
#      VCC                         : 1
#      XORCY                       : 4
# FlipFlops/Latches                : 7
#      FDR                         : 6
#      FDS                         : 1
# IO Buffers                       : 2
#      IBUF                        : 1
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                       7  out of    768     0%  
 Number of Slice Flip Flops:             7  out of   1536     0%  
 Number of 4 input LUTs:                 7  out of   1536     0%  
 Number of bonded IOBs:                  2  out of     96     2%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK(Mxor_CLK_Result1:O)            | NONE(*)(COUNT_3)       | 6     |
OUTCLK:Q                           | NONE                   | 1     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.140ns (Maximum Frequency: 194.553MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 6.788ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'Mxor_CLK_Result1:O'
Delay:               5.140ns (Levels of Logic = 1)
  Source:            COUNT_2 (FF)
  Destination:       COUNT_1 (FF)
  Source Clock:      Mxor_CLK_Result1:O rising
  Destination Clock: Mxor_CLK_Result1:O rising

  Data Path: COUNT_2 to COUNT_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   1.085   1.332  COUNT_2 (COUNT_2)
     LUT4:I0->O            4   0.549   1.440  COUNT_3_N381 (COUNT_0_3_N38)
     FDR:R                     0.734          COUNT_3
    ----------------------------------------
    Total                      5.140ns (2.368ns logic, 2.772ns route)
                                       (46.1% logic, 53.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'OUTCLK:Q'
Delay:               3.025ns (Levels of Logic = 0)
  Source:            divide2 (FF)
  Destination:       divide2 (FF)
  Source Clock:      OUTCLK:Q rising
  Destination Clock: OUTCLK:Q rising

  Data Path: divide2 to divide2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   1.085   1.206  divide2 (divide2)
     FDR:R                     0.734          divide2
    ----------------------------------------
    Total                      3.025ns (1.819ns logic, 1.206ns route)
                                       (60.1% logic, 39.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'Mxor_CLK_Result1:O'
Offset:              6.788ns (Levels of Logic = 1)
  Source:            OUTCLK_1 (FF)
  Destination:       OUTCLK (PAD)
  Source Clock:      Mxor_CLK_Result1:O rising

  Data Path: OUTCLK_1 to OUTCLK
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   1.085   1.035  OUTCLK_1 (OUTCLK_1)
     OBUF:I->O                 4.668          OUTCLK_OBUF (OUTCLK)
    ----------------------------------------
    Total                      6.788ns (5.753ns logic, 1.035ns route)
                                       (84.8% logic, 15.2% route)

=========================================================================
CPU : 4.13 / 6.22 s | Elapsed : 4.00 / 6.00 s
 
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Total memory usage is 69752 kilobytes