lz.vhf

自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的歌曲

-- VHDL model created from lz.sch - Thu Apr 12 19:44:15 2007


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity lz is
   port ( clk : in    std_logic; 
          q   : out   std_logic_vector (6 downto 0); 
          sp  : out   std_logic; 
          wx  : out   std_logic_vector (2 downto 0));
end lz;

architecture BEHAVIORAL of lz is
   signal XLXN_2 : std_logic;
   signal XLXN_3 : std_logic_vector (6 downto 0);
   signal XLXN_4 : std_logic_vector (4 downto 0);
   signal XLXN_5 : std_logic_vector (3 downto 0);
   signal XLXN_8 : std_logic;
   component fpq4hz
      port ( CLK : in    std_logic; 
             CP  : out   std_logic);
   end component;
   
   component song
      port ( clk4m   : in    std_logic; 
             clk4    : in    std_logic; 
             speaker : out   std_logic; 
             digit   : out   std_logic_vector (6 downto 0); 
             zero    : out   std_logic_vector (4 downto 0));
   end component;
   
   component ymq
      port ( A : in    std_logic_vector (3 downto 0); 
             Q : out   std_logic_vector (6 downto 0));
   end component;
   
   component xzq
      port ( clk : in    std_logic; 
             d   : in    std_logic_vector (6 downto 0); 
             z   : in    std_logic_vector (4 downto 0); 
             qq  : out   std_logic_vector (3 downto 0); 
             wx  : out   std_logic_vector (2 downto 0));
   end component;
   
   component fp01ms
      port ( CLK : in    std_logic; 
             CP  : out   std_logic);
   end component;
   
begin
   XLXI_2 : fpq4hz
      port map (CLK=>clk, CP=>XLXN_2);
   
   XLXI_3 : song
      port map (clk4=>XLXN_2, clk4m=>clk, digit(6 downto 0)=>XLXN_3(6 downto
            0), speaker=>sp, zero(4 downto 0)=>XLXN_4(4 downto 0));
   
   XLXI_5 : ymq
      port map (A(3 downto 0)=>XLXN_5(3 downto 0), Q(6 downto 0)=>q(6 downto
            0));
   
   XLXI_6 : xzq
      port map (clk=>XLXN_8, d(6 downto 0)=>XLXN_3(6 downto 0), z(4 downto
            0)=>XLXN_4(4 downto 0), qq(3 downto 0)=>XLXN_5(3 downto 0), wx(2
            downto 0)=>wx(2 downto 0));
   
   XLXI_7 : fp01ms
      port map (CLK=>clk, CP=>XLXN_8);
   
end BEHAVIORAL;