lz.syr

自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的歌曲

FlipFlop XLXI_3_counter_4 has been replicated 1 time(s)
FlipFlop XLXI_3_counter_3 has been replicated 1 time(s)
FlipFlop XLXI_3_counter_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : lz.ngr
Top Level Output File Name         : lz
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 12

Macro Statistics :
# ROMs                             : 1
#      256x7-bit ROM               : 1
# Registers                        : 13
#      1-bit register              : 6
#      24-bit register             : 5
#      3-bit register              : 1
#      4-bit register              : 1
# Counters                         : 1
#      13-bit up counter           : 1
# Multiplexers                     : 1
#      4-bit 4-to-1 multiplexer    : 1
# Tristates                        : 2
#      1-bit tristate buffer       : 2
# Adders/Subtractors               : 5
#      24-bit adder                : 5
# Comparators                      : 6
#      12-bit comparator greatequal: 1
#      12-bit comparator lessequal : 2
#      24-bit comparator greatequal: 1
#      24-bit comparator lessequal : 2

Cell Usage :
# BELS                             : 472
#      GND                         : 1
#      LUT1                        : 61
#      LUT1_D                      : 1
#      LUT1_L                      : 15
#      LUT2                        : 20
#      LUT2_L                      : 15
#      LUT3                        : 41
#      LUT3_D                      : 1
#      LUT3_L                      : 12
#      LUT4                        : 93
#      LUT4_D                      : 4
#      LUT4_L                      : 2
#      MUXCY                       : 120
#      MUXF5                       : 21
#      MUXF6                       : 10
#      VCC                         : 1
#      XORCY                       : 54
# FlipFlops/Latches                : 88
#      FD                          : 9
#      FDE                         : 13
#      FDR                         : 57
#      FDS                         : 2
#      LD                          : 7
# Tri-States                       : 2
#      BUFT                        : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 11
#      OBUF                        : 11
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                     150  out of    768    19%  
 Number of Slice Flip Flops:            88  out of   1536     5%  
 Number of 4 input LUTs:               265  out of   1536    17%  
 Number of bonded IOBs:                 11  out of     96    11%  
 Number of TBUFs:                        2  out of    768     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_5__n0001(XLXI_5__n00011:O)    | NONE(*)(XLXI_5_Q_3)    | 7     |
clk                                | BUFGP                  | 54    |
XLXI_3_carrier:Q                   | NONE                   | 3     |
XLXN_2(XLXI_2_I3_0:O)              | NONE(*)(XLXI_3_counter_4)| 15    |
XLXN_8(XLXI_7_I3_0:O)              | NONE(*)(XLXI_6_s_1)    | 9     |
-----------------------------------+------------------------+-------+
(*) These 3 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.644ns (Maximum Frequency: 103.691MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 6.959ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               9.644ns (Levels of Logic = 16)
  Source:            XLXI_3_divider_9 (FF)
  Destination:       XLXI_3_divider_12 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_3_divider_9 to XLXI_3_divider_12
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   1.085   1.206  XLXI_3_divider_9 (XLXI_3_divider_9)
     LUT4:I0->O            2   0.549   1.206  XLXI_3__n000412 (CHOICE744)
     LUT4_D:I0->O         13   0.549   2.250  XLXI_3__n000427 (XLXI_3__n0004)
     LUT3_L:I0->LO         1   0.549   0.000  XLXI_3_divider_inst_lut3_61 (XLXI_3_divider_inst_lut3_6)
     MUXCY:S->O            1   0.659   0.000  XLXI_3_divider_inst_cy_111 (XLXI_3_divider_inst_cy_111)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_divider_inst_cy_112 (XLXI_3_divider_inst_cy_112)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_divider_inst_cy_113 (XLXI_3_divider_inst_cy_113)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_divider_inst_cy_114 (XLXI_3_divider_inst_cy_114)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_divider_inst_cy_115 (XLXI_3_divider_inst_cy_115)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_divider_inst_cy_116 (XLXI_3_divider_inst_cy_116)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_divider_inst_cy_117 (XLXI_3_divider_inst_cy_117)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_divider_inst_cy_118 (XLXI_3_divider_inst_cy_118)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_divider_inst_cy_119 (XLXI_3_divider_inst_cy_119)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_divider_inst_cy_120 (XLXI_3_divider_inst_cy_120)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_divider_inst_cy_121 (XLXI_3_divider_inst_cy_121)
     MUXCY:CI->O           0   0.042   0.000  XLXI_3_divider_inst_cy_122 (XLXI_3_divider_inst_cy_122)
     XORCY:CI->O           1   0.420   0.000  XLXI_3_divider_inst_sum_56 (XLXI_3_divider_inst_sum_56)
     FDE:D                     0.709          XLXI_3_divider_12
    ----------------------------------------
    Total                      9.644ns (4.982ns logic, 4.662ns route)
                                       (51.7% logic, 48.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_3_carrier:Q'
Delay:               4.735ns (Levels of Logic = 1)
  Source:            XLXI_3_count_0 (FF)
  Destination:       XLXI_3_speaker (FF)
  Source Clock:      XLXI_3_carrier:Q rising
  Destination Clock: XLXI_3_carrier:Q rising

  Data Path: XLXI_3_count_0 to XLXI_3_speaker
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   1.085   1.332  XLXI_3_count_0 (XLXI_3_count_0)
     LUT2:I0->O            1   0.549   1.035  XLXI_3__n00171 (XLXI_3__n0017)
     FDR:R                     0.734          XLXI_3_speaker
    ----------------------------------------
    Total                      4.735ns (2.368ns logic, 2.367ns route)
                                       (50.0% logic, 50.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_2_I3_0:O'
Delay:               8.057ns (Levels of Logic = 2)
  Source:            XLXI_3_counter_5 (FF)
  Destination:       XLXI_3_counter_6 (FF)
  Source Clock:      XLXI_2_I3_0:O rising
  Destination Clock: XLXI_2_I3_0:O rising

  Data Path: XLXI_3_counter_5 to XLXI_3_counter_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             17   1.085   2.610  XLXI_3_counter_5 (XLXI_3_counter_5)
     LUT4_L:I3->LO         1   0.549   0.100  XLXI_3__n000622 (CHOICE675)
     LUT2:I1->O           15   0.549   2.430  XLXI_3__n000623 (XLXI_3__n0006)
     FDR:R                     0.734          XLXI_3_counter_0
    ----------------------------------------
    Total                      8.057ns (2.917ns logic, 5.140ns route)
                                       (36.2% logic, 63.8% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_7_I3_0:O'
Delay:               6.087ns (Levels of Logic = 2)
  Source:            XLXI_6_s_1 (FF)
  Destination:       XLXI_6_qq_2 (FF)
  Source Clock:      XLXI_7_I3_0:O rising
  Destination Clock: XLXI_7_I3_0:O rising

  Data Path: XLXI_6_s_1 to XLXI_6_qq_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             12   1.085   2.160  XLXI_6_s_1 (XLXI_6_s_1)
     LUT3:I0->O            1   0.549   1.035  XLXI_6_Mmux__n0002_inst_mux_f5_29_SW0 (N12528)
     LUT4:I1->O            1   0.549   0.000  XLXI_6_Mmux__n0002_inst_mux_f5_29 (XLXI_6__n0002<1>)
     FD:D                      0.709          XLXI_6_qq_1
    ----------------------------------------
    Total                      6.087ns (2.892ns logic, 3.195ns route)
                                       (47.5% logic, 52.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_3_carrier:Q'
Offset:              6.788ns (Levels of Logic = 1)
  Source:            XLXI_3_speaker (FF)
  Destination:       sp (PAD)
  Source Clock:      XLXI_3_carrier:Q rising

  Data Path: XLXI_3_speaker to sp
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   1.085   1.035  XLXI_3_speaker (XLXI_3_speaker)
     OBUF:I->O                 4.668          sp_OBUF (sp)
    ----------------------------------------
    Total                      6.788ns (5.753ns logic, 1.035ns route)
                                       (84.8% logic, 15.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_5__n00011:O'
Offset:              6.897ns (Levels of Logic = 1)
  Source:            XLXI_5_Q_6 (LATCH)
  Destination:       q<6> (PAD)
  Source Clock:      XLXI_5__n00011:O falling

  Data Path: XLXI_5_Q_6 to q<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   1.194   1.035  XLXI_5_Q_6 (XLXI_5_Q_6)
     OBUF:I->O                 4.668          q_6_OBUF (q<6>)
    ----------------------------------------
    Total                      6.897ns (5.862ns logic, 1.035ns route)
                                       (85.0% logic, 15.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_7_I3_0:O'
Offset:              6.959ns (Levels of Logic = 1)
  Source:            XLXI_6_wx_2 (FF)
  Destination:       wx<2> (PAD)
  Source Clock:      XLXI_7_I3_0:O rising

  Data Path: XLXI_6_wx_2 to wx<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   1.085   1.206  XLXI_6_wx_2 (XLXI_6_wx_2)
     OBUF:I->O                 4.668          wx_2_OBUF (wx<2>)
    ----------------------------------------
    Total                      6.959ns (5.753ns logic, 1.206ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
CPU : 10.91 / 12.33 s | Elapsed : 11.00 / 13.00 s
 
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Total memory usage is 61548 kilobytes