lz.syr

自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的歌曲

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.76 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.76 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: lz.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : lz.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : lz
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : lz
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : lz.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/dragon/VHDL/myboard/ok/lzhu/fpq4hz.vhdl in Library work.
Architecture behavioral of Entity fpq4hz is up to date.
Compiling vhdl file F:/dragon/VHDL/myboard/ok/lzhu/song.vhdl in Library work.
Entity <song> (Architecture <behavioral>) compiled.
Compiling vhdl file F:/dragon/VHDL/myboard/ok/lzhu/ymq.vhdl in Library work.
Architecture behavioral of Entity ymq is up to date.
Compiling vhdl file F:/dragon/VHDL/myboard/ok/lzhu/xzq.vhdl in Library work.
Architecture behavioral of Entity xzq is up to date.
Compiling vhdl file F:/dragon/VHDL/myboard/ok/lzhu/fp01ms.vhdl in Library work.
Architecture behavioral of Entity fp01ms is up to date.
Compiling vhdl file F:/dragon/VHDL/myboard/ok/lzhu/lz.vhf in Library work.
Entity <lz> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <lz> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - F:/dragon/VHDL/myboard/ok/lzhu/lz.vhf line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <lz> analyzed. Unit <lz> generated.

Analyzing Entity <fpq4hz> (Architecture <behavioral>).
Entity <fpq4hz> analyzed. Unit <fpq4hz> generated.

Analyzing Entity <song> (Architecture <behavioral>).
WARNING:Xst:819 - F:/dragon/VHDL/myboard/ok/lzhu/song.vhdl line 48: The following signals are missing in the process sensitivity list:
   counter.
Entity <song> analyzed. Unit <song> generated.

Analyzing Entity <ymq> (Architecture <behavioral>).
Entity <ymq> analyzed. Unit <ymq> generated.

Analyzing Entity <xzq> (Architecture <behavioral>).
WARNING:Xst:819 - F:/dragon/VHDL/myboard/ok/lzhu/xzq.vhdl line 23: The following signals are missing in the process sensitivity list:
   z<3>, d, z.
Entity <xzq> analyzed. Unit <xzq> generated.

Analyzing Entity <fp01ms> (Architecture <behavioral>).
Entity <fp01ms> analyzed. Unit <fp01ms> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fp01ms>.
    Related source file is F:/dragon/VHDL/myboard/ok/lzhu/fp01ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 12-bit comparator lessequal for signal <$n0002>.
    Found 12-bit comparator greatequal for signal <$n0007>.
    Found 12-bit comparator lessequal for signal <$n0008>.
    Found 12-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fp01ms> synthesized.


Synthesizing Unit <xzq>.
    Related source file is F:/dragon/VHDL/myboard/ok/lzhu/xzq.vhdl.
    Found 4-bit register for signal <qq>.
    Found 3-bit register for signal <wx>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0002> created at line 34.
    Found 2-bit up counter for signal <s>.
    Summary:
	inferred   1 Counter(s).
	inferred   7 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <xzq> synthesized.


Synthesizing Unit <ymq>.
    Related source file is F:/dragon/VHDL/myboard/ok/lzhu/ymq.vhdl.
WARNING:Xst:737 - Found 7-bit latch for signal <Q>.
Unit <ymq> synthesized.


Synthesizing Unit <song>.
    Related source file is F:/dragon/VHDL/myboard/ok/lzhu/song.vhdl.
    Found 256x7-bit ROM for signal <digit>.
    Found 1-bit register for signal <speaker>.
    Found 1-bit register for signal <carrier>.
    Found 2-bit up counter for signal <count>.
    Found 8-bit up counter for signal <counter>.
    Found 13-bit up counter for signal <divider>.
    Summary:
	inferred   1 ROM(s).
	inferred   3 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <song> synthesized.


Synthesizing Unit <fpq4hz>.
    Related source file is F:/dragon/VHDL/myboard/ok/lzhu/fpq4hz.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 24-bit comparator lessequal for signal <$n0002>.
    Found 24-bit comparator greatequal for signal <$n0007>.
    Found 24-bit comparator lessequal for signal <$n0008>.
    Found 24-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq4hz> synthesized.


Synthesizing Unit <lz>.
    Related source file is F:/dragon/VHDL/myboard/ok/lzhu/lz.vhf.
Unit <lz> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 256x7-bit ROM                     : 1
# Counters                         : 6
 13-bit up counter                 : 1
 24-bit up counter                 : 1
 8-bit up counter                  : 1
 12-bit up counter                 : 1
 2-bit up counter                  : 2
# Registers                        : 8
 1-bit register                    : 6
 3-bit register                    : 1
 4-bit register                    : 1
# Latches                          : 1
 7-bit latch                       : 1
# Comparators                      : 6
 24-bit comparator lessequal       : 2
 24-bit comparator greatequal      : 1
 12-bit comparator lessequal       : 2
 12-bit comparator greatequal      : 1
# Multiplexers                     : 1
 4-bit 4-to-1 multiplexer          : 1
# Tristates                        : 2
 1-bit tristate buffer             : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <lz> ...

Optimizing unit <fpq4hz> ...

Optimizing unit <ymq> ...

Optimizing unit <fp01ms> ...

Optimizing unit <song> ...

Optimizing unit <xzq> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx6.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lz, actual ratio is 19.
FlipFlop XLXI_3_counter_3 has been replicated 1 time(s)
FlipFlop XLXI_3_counter_2 has been replicated 1 time(s)
FlipFlop XLXI_3_counter_1 has been replicated 1 time(s)
FlipFlop XLXI_3_counter_0 has been replicated 1 time(s)