mult_add.v

Interpolation FIR Design Example for Stratix Devices

// megafunction wizard: %ALTMULT_ADD%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD 

// ============================================================
// File Name: mult_add.v
// Megafunction Name(s):
// 			ALTMULT_ADD
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************


//Copyright (C) 1991-2002 Altera Corporation
//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
//support information,  device programming or simulation file,  and any other
//associated  documentation or information  provided by  Altera  or a partner
//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
//other  use  of such  megafunction  design,  netlist,  support  information,
//device programming or simulation file,  or any other  related documentation
//or information  is prohibited  for  any  other purpose,  including, but not
//limited to  modification,  reverse engineering,  de-compiling, or use  with
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module mult_add (
	clock0,
	clock1,
	dataa_0,
	aclr3,
	datab_0,
	datab_1,
	ena0,
	datab_2,
	ena1,
	datab_3,
	shiftouta,
	result);

	input	  clock0;
	input	  clock1;
	input	[17:0]  dataa_0;
	input	  aclr3;
	input	[17:0]  datab_0;
	input	[17:0]  datab_1;
	input	  ena0;
	input	[17:0]  datab_2;
	input	  ena1;
	input	[17:0]  datab_3;
	output	[17:0]  shiftouta;
	output	[37:0]  result;

	wire [17:0] sub_wire0;
	wire [37:0] sub_wire1;
	wire [17:0] shiftouta = sub_wire0[17:0];
	wire [37:0] result = sub_wire1[37:0];
	wire [17:0] sub_wire2 = datab_1[17:0];
	wire [17:0] sub_wire4 = datab_0[17:0];
	wire [17:0] sub_wire5 = datab_2[17:0];
	wire [17:0] sub_wire6 = datab_3[17:0];
	wire [71:0] sub_wire3 = {sub_wire6[17:0], sub_wire5[17:0], sub_wire2[17:0], sub_wire4[17:0]};

	altmult_add	ALTMULT_ADD_component (
				.dataa (dataa_0),
				.datab (sub_wire3),
				.clock0 (clock0),
				.clock1 (clock1),
				.aclr3 (aclr3),
				.ena0 (ena0),
				.ena1 (ena1),
				.scanouta (sub_wire0),
				.result (sub_wire1));
	defparam
		ALTMULT_ADD_component.input_register_b2 = "CLOCK1",
		ALTMULT_ADD_component.input_register_a1 = "CLOCK0",
		ALTMULT_ADD_component.multiplier_register0 = "CLOCK1",
		ALTMULT_ADD_component.input_register_b3 = "CLOCK1",
		ALTMULT_ADD_component.input_register_a2 = "CLOCK0",
		ALTMULT_ADD_component.multiplier_register1 = "CLOCK1",
		ALTMULT_ADD_component.addnsub_multiplier_pipeline_aclr1 = "ACLR3",
		ALTMULT_ADD_component.input_register_a3 = "CLOCK0",
		ALTMULT_ADD_component.multiplier_register2 = "CLOCK1",
		ALTMULT_ADD_component.signed_aclr_a = "ACLR3",
		ALTMULT_ADD_component.signed_register_a = "CLOCK0",
		ALTMULT_ADD_component.number_of_multipliers = 4,
		ALTMULT_ADD_component.multiplier_register3 = "CLOCK1",
		ALTMULT_ADD_component.multiplier_aclr0 = "ACLR3",
		ALTMULT_ADD_component.addnsub_multiplier_pipeline_aclr3 = "ACLR3",
		ALTMULT_ADD_component.signed_aclr_b = "ACLR3",
		ALTMULT_ADD_component.signed_register_b = "CLOCK0",
		ALTMULT_ADD_component.multiplier_aclr1 = "ACLR3",
		ALTMULT_ADD_component.input_aclr_b0 = "ACLR3",
		ALTMULT_ADD_component.output_register = "CLOCK1",
		ALTMULT_ADD_component.representation_a = "SIGNED",
		ALTMULT_ADD_component.width_result = 38,
		ALTMULT_ADD_component.input_source_b0 = "DATAB",
		ALTMULT_ADD_component.multiplier_aclr2 = "ACLR3",
		ALTMULT_ADD_component.input_aclr_b1 = "ACLR3",
		ALTMULT_ADD_component.input_aclr_a0 = "ACLR3",
		ALTMULT_ADD_component.multiplier3_direction = "ADD",
		ALTMULT_ADD_component.addnsub_multiplier_register1 = "CLOCK0",
		ALTMULT_ADD_component.representation_b = "SIGNED",
		ALTMULT_ADD_component.input_source_b1 = "DATAB",
		ALTMULT_ADD_component.input_source_a0 = "SCANA",
		ALTMULT_ADD_component.multiplier_aclr3 = "ACLR3",
		ALTMULT_ADD_component.input_aclr_b2 = "ACLR3",
		ALTMULT_ADD_component.input_aclr_a1 = "ACLR3",
		ALTMULT_ADD_component.input_source_b2 = "DATAB",
		ALTMULT_ADD_component.input_source_a1 = "SCANA",
		ALTMULT_ADD_component.input_aclr_b3 = "ACLR3",
		ALTMULT_ADD_component.input_aclr_a2 = "ACLR3",
		ALTMULT_ADD_component.addnsub_multiplier_register3 = "CLOCK0",
		ALTMULT_ADD_component.addnsub_multiplier_aclr1 = "ACLR3",
		ALTMULT_ADD_component.output_aclr = "ACLR3",
		ALTMULT_ADD_component.input_source_b3 = "DATAB",
		ALTMULT_ADD_component.input_source_a2 = "SCANA",
		ALTMULT_ADD_component.input_aclr_a3 = "ACLR3",
		ALTMULT_ADD_component.input_source_a3 = "SCANA",
		ALTMULT_ADD_component.addnsub_multiplier_aclr3 = "ACLR3",
		ALTMULT_ADD_component.addnsub_multiplier_pipeline_register1 = "CLOCK0",
		ALTMULT_ADD_component.width_a = 18,
		ALTMULT_ADD_component.input_register_b0 = "CLOCK1",
		ALTMULT_ADD_component.width_b = 18,
		ALTMULT_ADD_component.input_register_b1 = "CLOCK1",
		ALTMULT_ADD_component.input_register_a0 = "CLOCK0",
		ALTMULT_ADD_component.addnsub_multiplier_pipeline_register3 = "CLOCK0",
		ALTMULT_ADD_component.multiplier1_direction = "ADD";


endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: SRCB1 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCA0 STRING "Shiftin input"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "1"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: SIGNA STRING "Signed"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "0"
// Retrieval info: PRIVATE: SRCB2 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCA1 STRING "Shiftin input"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT1 NUMERIC "0"
// Retrieval info: PRIVATE: MULT_REGOUT0 STRING "1"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"