speed.vhd

计费器设计中速度控制模块、里程计数模块、计费计数模块vhdl源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY speed IS
	PORT(
		clk,reset,start:IN STD_LOGIC;
		k:IN STD_LOGIC_VECTOR(4 downto 0);
		clkout:OUT STD_LOGIC);  
END speed;

ARCHITECTURE a OF speed IS
	SIGNAL count1:STD_LOGIC_VECTOR(1 downto 0);
	SIGNAL tempclk,clks:STD_LOGIC;
	SIGNAL kinside:STD_LOGIC_VECTOR(4 downto 0);

BEGIN
	kinside<="00000"-k;
clks_label:

PROCESS(reset,clk)
	variable count2:STD_LOGIC_VECTOR(4 downto 0);

BEGIN
	IF reset='1'  THEN
    	count2:="00000";
	ELSIF clk'event and clk='1' THEN
		if start='1'then
    		if count2=kinside then 
				count2:="00000";  
			end if;
			if not (k="00000") then 
				count2:=count2+1; 
			end if;
			if count2="00001" then 
				tempclk<=not tempclk; 
			end if;
		end if;
	END IF;
END PROCESS clks_label;
clkout<=tempclk;
END a;