_primary.vhd

来自「FPGA-CPLD_DesignTool(8-9-10)源代码请需要的朋友下载」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity tb is
    generic(
        eeprom_address  : integer := 80;
        i2c_address_base: integer := 0
    );
end tb;