module_a.plg

来自「FPGA-CPLD_DesignTool(8-9-10)源代码请需要的朋友下载」· PLG 代码 · 共 16 行

@P:  Worst Slack : 7.703
@P:  module_a|CLK_TOP - Estimated Frequency : 436.9 MHz
@P:  module_a|CLK_TOP - Requested Frequency : 100.0 MHz
@P:  module_a|CLK_TOP - Estimated Period : 2.289
@P:  module_a|CLK_TOP - Requested Period : 10.000
@P:  module_a|CLK_TOP - Slack : 7.711
@P:  module_a|MODA_CLK - Estimated Frequency : 435.3 MHz
@P:  module_a|MODA_CLK - Requested Frequency : 100.0 MHz
@P:  module_a|MODA_CLK - Estimated Period : 2.297
@P:  module_a|MODA_CLK - Requested Period : 10.000
@P:  module_a|MODA_CLK - Slack : 7.703
@P: module_a Part : xc2v40cs144-5
@P: module_a I/O Register bits : 0
@P: module_a Register bits (Non I/O) : 8 (1%)
@P: module_a Total Luts : 2 (0%)