📄 top_routed.par
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Release 5.2i - Par F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. :: Thu Mar 27 15:52:01 2003par -w top.ncd top_routed.ncd Constraints file: top.pcfLoading device database for application par from file "top.ncd". "top" is an NCD, version 2.37, device xc2v40, package cs144, speed -5Loading device for application par from file '2v40.nph' in environment
J:/eda/Xilinx.The STEPPING level for this design is 1.Device speed data version: PRODUCTION 1.114 2002-12-13.Resolved that IOB <modb_out> must be placed at site B6.Resolved that IOB <top2a_c> must be placed at site A4.Resolved that IOB <modb_clk_pad> must be placed at site D7.Resolved that IOB <moda_data> must be placed at site A5.Resolved that IOB <dll_rst> must be placed at site A3.Resolved that IOB <ipad_dll_clk_in> must be placed at site B4.Resolved that IOB <modb_data> must be placed at site C6.Resolved that IOB <mod_c_out> must be placed at site C8.Resolved that IOB <moda_clk_pad> must be placed at site D6.Resolved that IOB <top2b> must be placed at site A6.Resolved that IOB <modc_clk_pad> must be placed at site B7.Resolved that IOB <modc_out> must be placed at site B8.Resolved that IOB <obuft_out> must be placed at site C4.Resolved that IOB <modc_data> must be placed at site A8.Resolved that IOB <moda_out> must be placed at site D5.Resolved that DCM <dll_1> must be placed at site DCM_X0Y1.Resolved that BUFGMUX <bufg_modb/BUFG> must be placed at site BUFGMUX4S.Resolved that BUFGMUX <globalclk> must be placed at site BUFGMUX6S.Resolved that BUFGMUX <bufg_modc/BUFG> must be placed at site BUFGMUX1P.Resolved that BUFGMUX <bufg_moda/BUFG> must be placed at site BUFGMUX7P.Resolved that SLICE <b2c/PSEUDO_DRIVER> must be placed at site SLICE_X5Y10.Resolved that SLICE <a2c/PSEUDO_DRIVER> must be placed at site SLICE_X5Y14.Resolved that SLICE <a_and_c> must be placed at site SLICE_X7Y15.Resolved that SLICE <c2a/PSEUDO_LOAD> must be placed at site SLICE_X5Y4.Device utilization summary: Number of External IOBs 15 out of 88 17% Number of LOCed External IOBs 15 out of 15 100% Number of SLICEs 12 out of 256 4% Number of BUFGMUXs 4 out of 16 25% Number of DCMs 1 out of 4 25%Overall effort level (-ol): 2 (default)Placer effort level (-pl): 2 (default)Placer cost table entry (-t): 1Router effort level (-rl): 2 (default)Starting initial Timing Analysis. REAL time: 2 secs WARNING:Timing:2666 - Constraint ignored: TS_P2P = MAXDELAY FROM TIMEGRP "PADS"
TO TIMEGRP "PADS" 20 nS ; WARNING:Timing:2667 - ipad_dll_clk_in does not clock data to mod_c_outWARNING:Timing:2666 - Constraint ignored: COMP "mod_c_out" OFFSET = OUT 10 nS
AFTER COMP "ipad_dll_clk_in" ;WARNING:Timing:2667 - ipad_dll_clk_in does not clock data to moda_outWARNING:Timing:2666 - Constraint ignored: COMP "moda_out" OFFSET = OUT 10 nS
AFTER COMP "ipad_dll_clk_in" ;WARNING:Timing:2664 - ipad_dll_clk_in does not clock data from dll_rstWARNING:Timing:2666 - Constraint ignored: COMP "dll_rst" OFFSET = IN 10 nS
BEFORE COMP "ipad_dll_clk_in" ;WARNING:Timing:2664 - ipad_dll_clk_in does not clock data from top2bWARNING:Timing:2666 - Constraint ignored: COMP "top2b" OFFSET = IN 10 nS BEFORE
COMP "ipad_dll_clk_in" ;WARNING:Timing:2664 - ipad_dll_clk_in does not clock data from moda_dataWARNING:Timing:2666 - Constraint ignored: COMP "moda_data" OFFSET = IN 10 nS
BEFORE COMP "ipad_dll_clk_in" ;WARNING:Timing:2664 - ipad_dll_clk_in does not clock data from modc_clk_padWARNING:Timing:2666 - Constraint ignored: COMP "modc_clk_pad" OFFSET = IN 10 nS
BEFORE COMP "ipad_dll_clk_in" ;WARNING:Timing:2664 - ipad_dll_clk_in does not clock data from modb_dataWARNING:Timing:2666 - Constraint ignored: COMP "modb_data" OFFSET = IN 10 nS
BEFORE COMP "ipad_dll_clk_in" ;WARNING:Timing:2664 - ipad_dll_clk_in does not clock data from moda_clk_padWARNING:Timing:2666 - Constraint ignored: COMP "moda_clk_pad" OFFSET = IN 10 nS
BEFORE COMP "ipad_dll_clk_in" ;WARNING:Timing:2667 - ipad_dll_clk_in does not clock data to modb_outWARNING:Timing:2666 - Constraint ignored: COMP "modb_out" OFFSET = OUT 10 nS
AFTER COMP "ipad_dll_clk_in" ;WARNING:Timing:2667 - ipad_dll_clk_in does not clock data to obuft_outWARNING:Timing:2666 - Constraint ignored: COMP "obuft_out" OFFSET = OUT 10 nS
AFTER COMP "ipad_dll_clk_in" ;WARNING:Timing:2664 - ipad_dll_clk_in does not clock data from modb_clk_padWARNING:Timing:2666 - Constraint ignored: COMP "modb_clk_pad" OFFSET = IN 10 nS
BEFORE COMP "ipad_dll_clk_in" ;Finished initial Timing Analysis. REAL time: 5 secs Phase 1.1Phase 1.1 (Checksum:9896ff) REAL time: 5 secs WARNING: clk logic <ipad_dll_clk_in> locked elsewhere <B4>.WARNING: clk logic <moda_clk_pad> locked elsewhere <D6>.Phase 3.23WARNING:Place:35 - A clock IOB / clock component pair have been found that are
not placed at an optimal clock IOB / clock site pair. The clock component
<bufg_modc/BUFG> is placed at site BUFGMUX1P. The clock IO site that is
paired with this clock buffer site is A8. The IO component modc_clk_pad is
placed at site B7. This will not allow the use of the fast path between the
IO and the Clock buffer. You may want to analyze why this problem exists and
correct it. This is not an error so processing will continue.WARNING:Place:35 - A clock IOB / clock component pair have been found that are
not placed at an optimal clock IOB / clock site pair. The clock component
<bufg_moda/BUFG> is placed at site BUFGMUX7P. The clock IO site that is
paired with this clock buffer site is C6. The IO component moda_clk_pad is
placed at site D6. This will not allow the use of the fast path between the
IO and the Clock buffer. You may want to analyze why this problem exists and
correct it. This is not an error so processing will continue.Phase 3.23 (Checksum:1c9c37d) REAL time: 5 secs Phase 4.8..........Phase 4.8 (Checksum:98a7d7) REAL time: 5 secs Phase 5.5Phase 5.5 (Checksum:2faf07b) REAL time: 5 secs Phase 6.18Phase 6.18 (Checksum:39386fa) REAL time: 5 secs Phase 7.24Phase 7.24 (Checksum:42c1d79) REAL time: 5 secs Writing design to file top_routed.ncd.Total REAL time to placer completion: 5 secs Total CPU time to placer completion: 4 secs Starting Router REAL time: 5 secs Processing Modular Design.Phase 1: 43 unrouted; REAL time: 5 secs Phase 2: 24 unrouted; REAL time: 5 secs Phase 3: 4 unrouted; (0) REAL time: 5 secs Phase 4: 4 unrouted; (0) REAL time: 5 secs Phase 5: 4 unrouted; (0) REAL time: 5 secs Phase 6: 0 unrouted; (0) REAL time: 5 secs Finished Router REAL time: 5 secs Total REAL time to router completion: 5 secs Total CPU time to router completion: 4 secs Generating "par" statistics.**************************Generating Clock Report**************************+----------------------------+----------+--------+------------+-------------+| Clock Net | Resource | Fanout |Max Skew(ns)|Max Delay(ns)|+----------------------------+----------+--------+------------+-------------+| clk_top | Global | 5 | 0.002 | 0.560 |+----------------------------+----------+--------+------------+-------------+| modc_clk | Global | 4 | 0.002 | 0.562 |+----------------------------+----------+--------+------------+-------------+ The Delay Summary Report The Score for this design is: 5066The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 0.579 ns The Maximum Pin Delay is: 1.469 ns The Average Connection Delay on the 10 Worst Nets is: 0.417 ns Listing Pin Delays by value: (ns) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00 --------- --------- --------- --------- --------- --------- 40 3 0 0 0 0Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.-------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels-------------------------------------------------------------------------------- TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO | | | TIMEGRP "PADS" 20 nS | | | -------------------------------------------------------------------------------- TS_ipad_dll_clk_in = PERIOD TIMEGRP "ipad | 20.000ns | 2.171ns | 1 _dll_clk_in" 20 nS HIGH 50.000000 % | | | -------------------------------------------------------------------------------- COMP "modc_data" OFFSET = IN 10 nS BEFOR | 10.000ns | 1.586ns | 1 E COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "mod_c_out" OFFSET = OUT 10 nS AFTE | | | R COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "modc_out" OFFSET = OUT 20 nS AFTER | | | COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "modc_out" OFFSET = OUT 10 nS AFTER | 10.000ns | 6.553ns | 1 COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "moda_out" OFFSET = OUT 10 nS AFTER | | | COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "dll_rst" OFFSET = IN 10 nS BEFORE | | | COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "top2b" OFFSET = IN 10 nS BEFORE CO | | | MP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "top2a_c" OFFSET = IN 10 nS BEFORE | 10.000ns | 1.577ns | 1 COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "moda_data" OFFSET = IN 10 nS BEFOR | | | E COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "modc_clk_pad" OFFSET = IN 10 nS BE | | | FORE COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "modb_data" OFFSET = IN 10 nS BEFOR | | | E COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "moda_clk_pad" OFFSET = IN 10 nS BE | | | FORE COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "modb_out" OFFSET = OUT 10 nS AFTER | | | COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "obuft_out" OFFSET = OUT 10 nS AFTE | | | R COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "modb_clk_pad" OFFSET = IN 10 nS BE | | | FORE COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- OFFSET = IN 10 nS BEFORE COMP "ipad_dll_ | | | clk_in" | | | -------------------------------------------------------------------------------- OFFSET = OUT 10 nS AFTER COMP "ipad_dll_ | | | clk_in" | | | --------------------------------------------------------------------------------All constraints were met.All signals are completely routed.Total REAL time to par completion: 5 secs Total CPU time to par completion: 4 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - No errors found.Writing design to file top_routed.ncd.PAR done.⌨️ 快捷键说明
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