top_routed.twr

FPGA-CPLD_DesignTool(8-9-10)源代码请需要的朋友下载

--------------------------------------------------------------------------------
Release 5.2i - Trace F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

trce top_routed.ncd

Design file:              top_routed.ncd
Device,speed:             xc2v40,-5 (PRODUCTION 1.114 2002-12-13, STEPPING level 1)
Report level:             summary report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock ipad_dll_clk_in
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
modc_data   |    1.586(R)|   -1.349(R)|clk_top           |   0.000|
top2a_c     |    1.577(R)|   -1.340(R)|clk_top           |   0.000|
------------+------------+------------+------------------+--------+

Clock ipad_dll_clk_in to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
modc_out    |    6.553(R)|clk_top           |   0.000|
------------+------------+------------------+--------+

Clock modc_clk_pad to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
mod_c_out   |    9.086(R)|modc_clk          |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock ipad_dll_clk_in
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
ipad_dll_clk_in|    2.171|         |         |         |
modc_clk_pad   |    4.562|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock modc_clk_pad
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
ipad_dll_clk_in|    2.263|         |         |         |
modc_clk_pad   |    2.199|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Thu Mar 27 15:52:14 2003
--------------------------------------------------------------------------------