shixuljchf.vhd

时序乘法器,8位x8位,vhdl语言.仿真验证过了.多多交流!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shixuljchf  is
	generic(datawith:integer :=8);
	port(
		clk,start :in 	std_logic;
		a,b		:in 	std_logic_vector(datawith-1 downto 0);
		p		:out	std_logic_vector(datawith*2-1 downto 0);
		finished:buffer std_logic		
		);
end shixuljchf;

architecture aa of shixuljchf is

component addern8
	generic (datawith:integer :=8);
port
( 	cin : in std_logic;
	a,b : in std_logic_vector(datawith-1 downto 0);
	sum	: out std_logic_vector(datawith-1 downto 0);
	
	cout:	out std_logic
);
end component;

signal a_sig	:std_logic_vector(datawith-1 downto 0);
signal count	:integer range 0 to datawith+1 :=0;
signal count2	: integer range 0 to 2 :=0;
signal  adder_a,adder_b,adder_sum	:std_logic_vector(datawith-1 downto 0);
signal  adder_cin,adder_cout	:std_logic;
signal  zero:std_logic_vector(datawith-1 downto 0);
signal  p_sig:std_logic_vector(datawith*2-1 downto 0);

begin
c1:addern8
port map(
	cin=>adder_cin,
	a=>adder_a,
	b=>adder_b,
	sum=>adder_sum,
	cout=>adder_cout
);

process(clk)
begin
	if(clk'event and clk='0')then 
		if (count =0 )then--and count2=0
			p_sig(datawith-1 downto 0)<=zero;
			p_sig(datawith*2-1 downto datawith)<=zero;
		elsif (a_sig(0)='1' and count2=0) then
		elsif ( count2=1) then  --anda_sig(1)='1' 
			p_sig(datawith*2-1 downto datawith)<=adder_sum;
		elsif (count/=9  and count2=2) then
			p_sig(datawith*2-2 downto 0)<=p_sig(datawith*2-1 downto 1);
			p_sig(datawith*2-1 )<= adder_cout;
		end if;
	end if;
end process;

process(clk)
begin
	if (clk'event and clk='1')then
		if (a_sig(0)='1') then
			adder_a<=p_sig(datawith*2-1 downto datawith);
			adder_b<=b;
			adder_cin<='0';
		else 
			adder_a<=p_sig(datawith*2-1 downto datawith);
			adder_b<=zero;
			adder_cin<='0';
		end if;
	end if;
end process;

process(clk)
begin
	if (start='1' ) then --and finished='0'
		count<=0;
		count2<=0;
		finished<='0';
	elsif (clk'event and clk ='1') then
		if (count=9 and count2=2) then
			count<=count;
			count2<=count2;
			finished<='1';
		elsif (count2=2) then
			count2<=0;
			count<=count+1;
			finished<='0';
		else 
			count2<=count2+1;
			finished <='0';
		end if;
	end if;
end process;

process(clk)
begin
	if(clk'event and clk='1')then 
		if (count=0) then
			a_sig<= a;
		elsif(count2=2) then
 			a_sig(datawith-2 downto 0)<=a_sig(datawith-1 downto 1);
			a_sig(datawith-1 )<='0';
		else 
			a_sig<=a_sig;
		end if;
	else
		a_sig<=a_sig;
	end if;
end process;

process(finished)
begin
	if (finished='1')then
		p<=p_sig;
	end if;
end process;

g1:for i in 0 to datawith-1 generate
   	zero(i)<='0';
end generate;
end aa;