addern8.vhd

来自「时序乘法器,8位x8位,vhdl语言.仿真验证过了.多多交流!」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;

entity addern8 is
generic (datawith:integer :=8);
port
( 	cin : in std_logic;
	a,b : in std_logic_vector(datawith-1 downto 0);
	sum	: out std_logic_vector(datawith-1 downto 0);
	cout:	out std_logic
);
end addern8;

architecture aa of addern8 is 
component adder 
port(
	a,b,cin		:in std_logic;
	s,cout		:out std_logic
);
end component;

signal cout_temp : std_logic_vector(datawith-1 downto 0);

begin

g1:for i in 1 to datawith-1 generate 
	adder_portmap: adder port map(a(i),b(i),cout_temp(i-1),sum(i),cout_temp(i));
end generate;

	adder0_portmap: adder port map(a(0),b(0),cin,sum(0),cout_temp(0));
	cout<=cout_temp(datawith-1);
end aa;