adder.vhd

来自「时序乘法器,8位x8位,vhdl语言.仿真验证过了.多多交流!」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;

entity adder is 
port(
	a,b,cin		:in std_logic;
	s,cout		:out std_logic
);
end adder;

architecture aa of adder is

signal p,g:std_logic;
begin
  	p<=a xor  b;
	g<=a and b;
	s<=p xor cin ;
	cout<= g or (p and cin);
end aa;