test_double3.map.eqn

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K1_RAMTMP1[6]_lut_out = K1L55 & K1L85 & K1_RAMTMP1[6] # !K1L55 & A1L61;
K1_RAMTMP1[6] = DFFEA(K1_RAMTMP1[6]_lut_out, !CLK, VCC, , K1L04, , );


--K1_RAMTMP1[5] is BUS_51:inst9|RAMTMP1[5]
--operation mode is normal

K1_RAMTMP1[5]_lut_out = K1L55 & K1L85 & K1_RAMTMP1[5] # !K1L55 & A1L71;
K1_RAMTMP1[5] = DFFEA(K1_RAMTMP1[5]_lut_out, !CLK, VCC, , K1L04, , );


--K1_RAMTMP1[4] is BUS_51:inst9|RAMTMP1[4]
--operation mode is normal

K1_RAMTMP1[4]_lut_out = K1L55 & K1L85 & K1_RAMTMP1[4] # !K1L55 & A1L81;
K1_RAMTMP1[4] = DFFEA(K1_RAMTMP1[4]_lut_out, !CLK, VCC, , K1L04, , );


--K1_RAMTMP1[3] is BUS_51:inst9|RAMTMP1[3]
--operation mode is normal

K1_RAMTMP1[3]_lut_out = K1L55 & K1L85 & K1_RAMTMP1[3] # !K1L55 & A1L91;
K1_RAMTMP1[3] = DFFEA(K1_RAMTMP1[3]_lut_out, !CLK, VCC, , K1L04, , );


--K1_RAMTMP1[2] is BUS_51:inst9|RAMTMP1[2]
--operation mode is normal

K1_RAMTMP1[2]_lut_out = K1L55 & K1L85 & K1_RAMTMP1[2] # !K1L55 & A1L02;
K1_RAMTMP1[2] = DFFEA(K1_RAMTMP1[2]_lut_out, !CLK, VCC, , K1L04, , );


--K1_RAMTMP1[1] is BUS_51:inst9|RAMTMP1[1]
--operation mode is normal

K1_RAMTMP1[1]_lut_out = K1L55 & K1L85 & K1_RAMTMP1[1] # !K1L55 & A1L12;
K1_RAMTMP1[1] = DFFEA(K1_RAMTMP1[1]_lut_out, !CLK, VCC, , K1L04, , );


--K1_RAMTMP1[0] is BUS_51:inst9|RAMTMP1[0]
--operation mode is normal

K1_RAMTMP1[0]_lut_out = K1L55 & K1L85 & K1_RAMTMP1[0] # !K1L55 & A1L22;
K1_RAMTMP1[0] = DFFEA(K1_RAMTMP1[0]_lut_out, !CLK, VCC, , K1L04, , );


--K1L75 is BUS_51:inst9|reduce_nor~3
--operation mode is normal

K1L75 = !K1L06 # !K1_LATCH_ADDRES[2] # !K1_LATCH_ADDRES[1] # !K1_LATCH_ADDRES[0];


--K1L65 is BUS_51:inst9|reduce_nor~2
--operation mode is normal

K1L65 = K1_LATCH_ADDRES[0] # !K1L06 # !K1_LATCH_ADDRES[2] # !K1_LATCH_ADDRES[1];


--K1L35 is BUS_51:inst9|RAMTMP3[7]~16
--operation mode is normal

K1L35 = !K1L45 & K1L55 & K1L65 & K1L12;


--D1_REG_Q[5] is generator_accB:inst3|REG_Q[5]
--operation mode is arithmetic

D1_REG_Q[5]_carry_eqn = D1L11;
D1_REG_Q[5]_lut_out = D1_REG_Q[5] $ K1_RAMTMP1[5] $ D1_REG_Q[5]_carry_eqn;
D1_REG_Q[5] = DFFEA(D1_REG_Q[5]_lut_out, J1_CLK, !K1_TMP, , , , );

--D1L31 is generator_accB:inst3|REG_Q[5]~COUT
--operation mode is arithmetic

D1L31 = CARRY(D1_REG_Q[5] & !K1_RAMTMP1[5] & !D1L11 # !D1_REG_Q[5] & (!D1L11 # !K1_RAMTMP1[5]));


--K1L05 is BUS_51:inst9|RAMTMP2[7]~588
--operation mode is normal

K1L05 = !K1L45 & K1L55 & !CS & !WR;


--D1_REG_Q[4] is generator_accB:inst3|REG_Q[4]
--operation mode is arithmetic

D1_REG_Q[4]_carry_eqn = D1L9;
D1_REG_Q[4]_lut_out = D1_REG_Q[4] $ K1_RAMTMP1[4] $ !D1_REG_Q[4]_carry_eqn;
D1_REG_Q[4] = DFFEA(D1_REG_Q[4]_lut_out, J1_CLK, !K1_TMP, , , , );

--D1L11 is generator_accB:inst3|REG_Q[4]~COUT
--operation mode is arithmetic

D1L11 = CARRY(D1_REG_Q[4] & (K1_RAMTMP1[4] # !D1L9) # !D1_REG_Q[4] & K1_RAMTMP1[4] & !D1L9);


--D1_REG_Q[3] is generator_accB:inst3|REG_Q[3]
--operation mode is arithmetic

D1_REG_Q[3]_carry_eqn = D1L7;
D1_REG_Q[3]_lut_out = D1_REG_Q[3] $ K1_RAMTMP1[3] $ D1_REG_Q[3]_carry_eqn;
D1_REG_Q[3] = DFFEA(D1_REG_Q[3]_lut_out, J1_CLK, !K1_TMP, , , , );

--D1L9 is generator_accB:inst3|REG_Q[3]~COUT
--operation mode is arithmetic

D1L9 = CARRY(D1_REG_Q[3] & !K1_RAMTMP1[3] & !D1L7 # !D1_REG_Q[3] & (!D1L7 # !K1_RAMTMP1[3]));


--D1_REG_Q[2] is generator_accB:inst3|REG_Q[2]
--operation mode is arithmetic

D1_REG_Q[2]_carry_eqn = D1L5;
D1_REG_Q[2]_lut_out = D1_REG_Q[2] $ K1_RAMTMP1[2] $ !D1_REG_Q[2]_carry_eqn;
D1_REG_Q[2] = DFFEA(D1_REG_Q[2]_lut_out, J1_CLK, !K1_TMP, , , , );

--D1L7 is generator_accB:inst3|REG_Q[2]~COUT
--operation mode is arithmetic

D1L7 = CARRY(D1_REG_Q[2] & (K1_RAMTMP1[2] # !D1L5) # !D1_REG_Q[2] & K1_RAMTMP1[2] & !D1L5);


--D1_REG_Q[1] is generator_accB:inst3|REG_Q[1]
--operation mode is arithmetic

D1_REG_Q[1]_carry_eqn = D1L3;
D1_REG_Q[1]_lut_out = D1_REG_Q[1] $ K1_RAMTMP1[1] $ D1_REG_Q[1]_carry_eqn;
D1_REG_Q[1] = DFFEA(D1_REG_Q[1]_lut_out, J1_CLK, !K1_TMP, , , , );

--D1L5 is generator_accB:inst3|REG_Q[1]~COUT
--operation mode is arithmetic

D1L5 = CARRY(D1_REG_Q[1] & !K1_RAMTMP1[1] & !D1L3 # !D1_REG_Q[1] & (!D1L3 # !K1_RAMTMP1[1]));


--D1_REG_Q[0] is generator_accB:inst3|REG_Q[0]
--operation mode is arithmetic

D1_REG_Q[0]_lut_out = D1_REG_Q[0] $ K1_RAMTMP1[0];
D1_REG_Q[0] = DFFEA(D1_REG_Q[0]_lut_out, J1_CLK, !K1_TMP, , , , );

--D1L3 is generator_accB:inst3|REG_Q[0]~COUT
--operation mode is arithmetic

D1L3 = CARRY(D1_REG_Q[0] & K1_RAMTMP1[0]);


--K1L04 is BUS_51:inst9|RAMTMP1[7]~603
--operation mode is normal

K1L04 = !CS & !WR & !K1L45;


--P2[4] is P2[4]
--operation mode is input

P2[4] = INPUT();


--P2[3] is P2[3]
--operation mode is input

P2[3] = INPUT();


--P2[2] is P2[2]
--operation mode is input

P2[2] = INPUT();


--P2[1] is P2[1]
--operation mode is input

P2[1] = INPUT();


--P2[0] is P2[0]
--operation mode is input

P2[0] = INPUT();


--CLK is CLK
--operation mode is input

CLK = INPUT();


--CS is CS
--operation mode is input

CS = INPUT();


--WR is WR
--operation mode is input

WR = INPUT();


--ALE is ALE
--operation mode is input

ALE = INPUT();


--RD is RD
--operation mode is input

RD = INPUT();


--XFER is XFER
--operation mode is output

XFER = OUTPUT(GND);


--DA1CS is DA1CS
--operation mode is output

DA1CS = OUTPUT(GND);


--DA2CS is DA2CS
--operation mode is output

DA2CS = OUTPUT(GND);


--WRN is WRN
--operation mode is output

WRN = OUTPUT(GND);


--Q1[7] is Q1[7]
--operation mode is output

Q1[7] = OUTPUT(G1_TEMP_Q_1[7]);


--Q1[6] is Q1[6]
--operation mode is output

Q1[6] = OUTPUT(G1_TEMP_Q_1[6]);


--Q1[5] is Q1[5]
--operation mode is output

Q1[5] = OUTPUT(G1_TEMP_Q_1[5]);


--Q1[4] is Q1[4]
--operation mode is output

Q1[4] = OUTPUT(G1_TEMP_Q_1[4]);


--Q1[3] is Q1[3]
--operation mode is output

Q1[3] = OUTPUT(G1_TEMP_Q_1[3]);


--Q1[2] is Q1[2]
--operation mode is output

Q1[2] = OUTPUT(G1_TEMP_Q_1[2]);


--Q1[1] is Q1[1]
--operation mode is output

Q1[1] = OUTPUT(G1_TEMP_Q_1[1]);


--Q1[0] is Q1[0]
--operation mode is output

Q1[0] = OUTPUT(G1_TEMP_Q_1[0]);


--Q2[7] is Q2[7]
--operation mode is output

Q2[7] = OUTPUT(H1_TEMP_Q_1[7]);


--Q2[6] is Q2[6]
--operation mode is output

Q2[6] = OUTPUT(H1_TEMP_Q_1[6]);


--Q2[5] is Q2[5]
--operation mode is output

Q2[5] = OUTPUT(H1_TEMP_Q_1[5]);


--Q2[4] is Q2[4]
--operation mode is output

Q2[4] = OUTPUT(H1_TEMP_Q_1[4]);


--Q2[3] is Q2[3]
--operation mode is output

Q2[3] = OUTPUT(H1_TEMP_Q_1[3]);


--Q2[2] is Q2[2]
--operation mode is output

Q2[2] = OUTPUT(H1_TEMP_Q_1[2]);


--Q2[1] is Q2[1]
--operation mode is output

Q2[1] = OUTPUT(H1_TEMP_Q_1[1]);


--Q2[0] is Q2[0]
--operation mode is output

Q2[0] = OUTPUT(H1_TEMP_Q_1[0]);


--A1L51 is P0~0
--operation mode is bidir

A1L51 = P0[7];

--P0[7] is P0[7]
--operation mode is bidir

P0[7]_tri_out = TRI(K1_P0_OUT[7], K1_GX);
P0[7] = BIDIR(P0[7]_tri_out);


--A1L61 is P0~1
--operation mode is bidir

A1L61 = P0[6];

--P0[6] is P0[6]
--operation mode is bidir

P0[6]_tri_out = TRI(K1_P0_OUT[6], K1_GX);
P0[6] = BIDIR(P0[6]_tri_out);


--A1L71 is P0~2
--operation mode is bidir

A1L71 = P0[5];

--P0[5] is P0[5]
--operation mode is bidir

P0[5]_tri_out = TRI(K1_P0_OUT[5], K1_GX);
P0[5] = BIDIR(P0[5]_tri_out);


--A1L81 is P0~3
--operation mode is bidir

A1L81 = P0[4];

--P0[4] is P0[4]
--operation mode is bidir

P0[4]_tri_out = TRI(K1_P0_OUT[4], K1_GX);
P0[4] = BIDIR(P0[4]_tri_out);


--A1L91 is P0~4
--operation mode is bidir

A1L91 = P0[3];

--P0[3] is P0[3]
--operation mode is bidir

P0[3]_tri_out = TRI(K1_P0_OUT[3], K1_GX);
P0[3] = BIDIR(P0[3]_tri_out);


--A1L02 is P0~5
--operation mode is bidir

A1L02 = P0[2];

--P0[2] is P0[2]
--operation mode is bidir

P0[2]_tri_out = TRI(K1_P0_OUT[2], K1_GX);
P0[2] = BIDIR(P0[2]_tri_out);


--A1L12 is P0~6
--operation mode is bidir

A1L12 = P0[1];

--P0[1] is P0[1]
--operation mode is bidir

P0[1]_tri_out = TRI(K1_P0_OUT[1], K1_GX);
P0[1] = BIDIR(P0[1]_tri_out);


--A1L22 is P0~7
--operation mode is bidir

A1L22 = P0[0];

--P0[0] is P0[0]
--operation mode is bidir

P0[0]_tri_out = TRI(K1_P0_OUT[0], K1_GX);
P0[0] = BIDIR(P0[0]_tri_out);