generator_add.vhd

来自「DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫」· VHDL 代码 · 共 31 行

------------------------------------------------------------------------------------
-- DESCRIPTION   :  cascadable Adder
--                  Width: 6
--
-- 
------------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity generator_add is
	port (
        A : in std_logic_vector (15 downto 0);
	    B : in std_logic_vector (15 downto 0);
		Q : out std_logic_vector (8 downto 0)
	);
end entity;

--}} End of automatically maintained section

architecture add_anGen_arch of generator_add is
begin
	process (A ,B)
	begin
		Q <= A(15 downto 7) + B(15 downto 7);
	end process;

end architecture add_anGen_arch;