generator_accb.vhd

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------------------------------------------------------------------------------------
-- DESCRIPTION   :  Cascadable Accumulator with Adder
--                  Width : 6
--                  CLK (CLK) active : high
--                  CLR (CLR) active : high
--                  CLR (CLR) type : asynchronous
--                  CE (CE) active : high
--
------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity generator_accB is
	port (
		CLK : in std_logic;
	    CLR : in std_logic;
		A : in std_logic_vector (15 downto 0);
		Q : out std_logic_vector (15 downto 0);
        M: OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
	);
end entity;



architecture acc_arch of generator_accB is
signal REG_Q  : std_logic_vector (15 downto 0);
signal TEMP_Q : std_logic_vector (15 downto 0);
begin
	process (REG_Q)
	begin
		TEMP_Q <= REG_Q + A;
	end process;

	process(CLK,CLR)
	begin
		if CLR = '1' then
			REG_Q <= "0000000000000000";
		ELSif rising_edge(CLK) then
				REG_Q <= TEMP_Q;
		end if;
	end process;

	Q <= REG_Q;
    M<=REG_Q(15 DOWNTO 7);

end architecture;