test_double3.hier_info

DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫屏锯齿波。频率可用键盘精确控制

rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_uou:auto_generated.address_a[0]
address_a[1] => altsyncram_uou:auto_generated.address_a[1]
address_a[2] => altsyncram_uou:auto_generated.address_a[2]
address_a[3] => altsyncram_uou:auto_generated.address_a[3]
address_a[4] => altsyncram_uou:auto_generated.address_a[4]
address_a[5] => altsyncram_uou:auto_generated.address_a[5]
address_a[6] => altsyncram_uou:auto_generated.address_a[6]
address_a[7] => altsyncram_uou:auto_generated.address_a[7]
address_a[8] => altsyncram_uou:auto_generated.address_a[8]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_uou:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_uou:auto_generated.q_a[0]
q_a[1] <= altsyncram_uou:auto_generated.q_a[1]
q_a[2] <= altsyncram_uou:auto_generated.q_a[2]
q_a[3] <= altsyncram_uou:auto_generated.q_a[3]
q_a[4] <= altsyncram_uou:auto_generated.q_a[4]
q_a[5] <= altsyncram_uou:auto_generated.q_a[5]
q_a[6] <= altsyncram_uou:auto_generated.q_a[6]
q_a[7] <= altsyncram_uou:auto_generated.q_a[7]
q_b[0] <= <UNC>


|test_double3|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_uou:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT


|test_double3|MUX2S:inst5
S1[0] => M~16.DATAB
S1[1] => M~14.DATAB
S1[2] => M~12.DATAB
S1[3] => M~10.DATAB
S1[4] => M~8.DATAB
S1[5] => M~6.DATAB
S1[6] => M~4.DATAB
S1[7] => M~2.DATAB
S1[8] => M~0.DATAB
S2[0] => M~16.DATAA
S2[1] => M~14.DATAA
S2[2] => M~12.DATAA
S2[3] => M~10.DATAA
S2[4] => M~8.DATAA
S2[5] => M~6.DATAA
S2[6] => M~4.DATAA
S2[7] => M~2.DATAA
S2[8] => M~0.DATAA
M[0] <= M~17.DB_MAX_OUTPUT_PORT_TYPE
M[1] <= M~15.DB_MAX_OUTPUT_PORT_TYPE
M[2] <= M~13.DB_MAX_OUTPUT_PORT_TYPE
M[3] <= M~11.DB_MAX_OUTPUT_PORT_TYPE
M[4] <= M~9.DB_MAX_OUTPUT_PORT_TYPE
M[5] <= M~7.DB_MAX_OUTPUT_PORT_TYPE
M[6] <= M~5.DB_MAX_OUTPUT_PORT_TYPE
M[7] <= M~3.DB_MAX_OUTPUT_PORT_TYPE
M[8] <= M~1.DB_MAX_OUTPUT_PORT_TYPE
CLK => M~0.OUTPUTSELECT
CLK => M~2.OUTPUTSELECT
CLK => M~4.OUTPUTSELECT
CLK => M~6.OUTPUTSELECT
CLK => M~8.OUTPUTSELECT
CLK => M~10.OUTPUTSELECT
CLK => M~12.OUTPUTSELECT
CLK => M~14.OUTPUTSELECT
CLK => M~16.OUTPUTSELECT


|test_double3|generator_add:inst4
A[0] => ~NO_FANOUT~
A[1] => ~NO_FANOUT~
A[2] => ~NO_FANOUT~
A[3] => ~NO_FANOUT~
A[4] => ~NO_FANOUT~
A[5] => ~NO_FANOUT~
A[6] => ~NO_FANOUT~
A[7] => add~0.IN9
A[8] => add~0.IN8
A[9] => add~0.IN7
A[10] => add~0.IN6
A[11] => add~0.IN5
A[12] => add~0.IN4
A[13] => add~0.IN3
A[14] => add~0.IN2
A[15] => add~0.IN1
B[0] => ~NO_FANOUT~
B[1] => ~NO_FANOUT~
B[2] => ~NO_FANOUT~
B[3] => ~NO_FANOUT~
B[4] => ~NO_FANOUT~
B[5] => ~NO_FANOUT~
B[6] => ~NO_FANOUT~
B[7] => add~0.IN18
B[8] => add~0.IN17
B[9] => add~0.IN16
B[10] => add~0.IN15
B[11] => add~0.IN14
B[12] => add~0.IN13
B[13] => add~0.IN12
B[14] => add~0.IN11
B[15] => add~0.IN10
Q[0] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= add~0.DB_MAX_OUTPUT_PORT_TYPE


|test_double3|generator_accB:inst3
CLK => REG_Q[14].CLK
CLK => REG_Q[13].CLK
CLK => REG_Q[12].CLK
CLK => REG_Q[11].CLK
CLK => REG_Q[10].CLK
CLK => REG_Q[9].CLK
CLK => REG_Q[8].CLK
CLK => REG_Q[7].CLK
CLK => REG_Q[6].CLK
CLK => REG_Q[5].CLK
CLK => REG_Q[4].CLK
CLK => REG_Q[3].CLK
CLK => REG_Q[2].CLK
CLK => REG_Q[1].CLK
CLK => REG_Q[0].CLK
CLK => REG_Q[15].CLK
CLR => REG_Q[14].ACLR
CLR => REG_Q[13].ACLR
CLR => REG_Q[12].ACLR
CLR => REG_Q[11].ACLR
CLR => REG_Q[10].ACLR
CLR => REG_Q[9].ACLR
CLR => REG_Q[8].ACLR
CLR => REG_Q[7].ACLR
CLR => REG_Q[6].ACLR
CLR => REG_Q[5].ACLR
CLR => REG_Q[4].ACLR
CLR => REG_Q[3].ACLR
CLR => REG_Q[2].ACLR
CLR => REG_Q[1].ACLR
CLR => REG_Q[0].ACLR
CLR => REG_Q[15].ACLR
A[0] => add~0.IN16
A[1] => add~0.IN15
A[2] => add~0.IN14
A[3] => add~0.IN13
A[4] => add~0.IN12
A[5] => add~0.IN11
A[6] => add~0.IN10
A[7] => add~0.IN9
A[8] => add~0.IN8
A[9] => add~0.IN7
A[10] => add~0.IN6
A[11] => add~0.IN5
A[12] => add~0.IN4
A[13] => add~0.IN3
A[14] => add~0.IN2
A[15] => add~0.IN1
Q[0] <= REG_Q[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= REG_Q[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= REG_Q[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= REG_Q[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= REG_Q[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= REG_Q[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= REG_Q[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= REG_Q[7].DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= REG_Q[8].DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= REG_Q[9].DB_MAX_OUTPUT_PORT_TYPE
Q[10] <= REG_Q[10].DB_MAX_OUTPUT_PORT_TYPE
Q[11] <= REG_Q[11].DB_MAX_OUTPUT_PORT_TYPE
Q[12] <= REG_Q[12].DB_MAX_OUTPUT_PORT_TYPE
Q[13] <= REG_Q[13].DB_MAX_OUTPUT_PORT_TYPE
Q[14] <= REG_Q[14].DB_MAX_OUTPUT_PORT_TYPE
Q[15] <= REG_Q[15].DB_MAX_OUTPUT_PORT_TYPE
M[0] <= REG_Q[7].DB_MAX_OUTPUT_PORT_TYPE
M[1] <= REG_Q[8].DB_MAX_OUTPUT_PORT_TYPE
M[2] <= REG_Q[9].DB_MAX_OUTPUT_PORT_TYPE
M[3] <= REG_Q[10].DB_MAX_OUTPUT_PORT_TYPE
M[4] <= REG_Q[11].DB_MAX_OUTPUT_PORT_TYPE
M[5] <= REG_Q[12].DB_MAX_OUTPUT_PORT_TYPE
M[6] <= REG_Q[13].DB_MAX_OUTPUT_PORT_TYPE
M[7] <= REG_Q[14].DB_MAX_OUTPUT_PORT_TYPE
M[8] <= REG_Q[15].DB_MAX_OUTPUT_PORT_TYPE


|test_double3|generator_reg82:inst7
CLR => TEMP_Q_1[6].ACLR
CLR => TEMP_Q_1[5].ACLR
CLR => TEMP_Q_1[4].ACLR
CLR => TEMP_Q_1[3].ACLR
CLR => TEMP_Q_1[2].ACLR
CLR => TEMP_Q_1[1].ACLR
CLR => TEMP_Q_1[0].ACLR
CLR => TEMP_Q_1[7].ACLR
CLKK => TEMP_Q_1[6].CLK
CLKK => TEMP_Q_1[5].CLK
CLKK => TEMP_Q_1[4].CLK
CLKK => TEMP_Q_1[3].CLK
CLKK => TEMP_Q_1[2].CLK
CLKK => TEMP_Q_1[1].CLK
CLKK => TEMP_Q_1[0].CLK
CLKK => TEMP_Q_1[7].CLK
DATA[0] => TEMP_Q_1[0].DATAIN
DATA[1] => TEMP_Q_1[1].DATAIN
DATA[2] => TEMP_Q_1[2].DATAIN
DATA[3] => TEMP_Q_1[3].DATAIN
DATA[4] => TEMP_Q_1[4].DATAIN
DATA[5] => TEMP_Q_1[5].DATAIN
DATA[6] => TEMP_Q_1[6].DATAIN
DATA[7] => TEMP_Q_1[7].DATAIN
Q2[0] <= TEMP_Q_1[0].DB_MAX_OUTPUT_PORT_TYPE
Q2[1] <= TEMP_Q_1[1].DB_MAX_OUTPUT_PORT_TYPE
Q2[2] <= TEMP_Q_1[2].DB_MAX_OUTPUT_PORT_TYPE
Q2[3] <= TEMP_Q_1[3].DB_MAX_OUTPUT_PORT_TYPE
Q2[4] <= TEMP_Q_1[4].DB_MAX_OUTPUT_PORT_TYPE
Q2[5] <= TEMP_Q_1[5].DB_MAX_OUTPUT_PORT_TYPE
Q2[6] <= TEMP_Q_1[6].DB_MAX_OUTPUT_PORT_TYPE
Q2[7] <= TEMP_Q_1[7].DB_MAX_OUTPUT_PORT_TYPE