test_double3.map.qmsg

DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫屏锯齿波。频率可用键盘精确控制

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "d:/altera/quartus41/libraries/megafunctions/altsyncram.tdf" "altsyncram" "" { Text "d:/altera/quartus41/libraries/megafunctions/altsyncram.tdf" 431 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_uou.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_uou.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_uou " "Info: Found entity 1: altsyncram_uou" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/altsyncram_uou.tdf" "altsyncram_uou" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/db/altsyncram_uou.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a generator_accb.vhd(35) " "Warning: VHDL Process Statement warning at generator_accb.vhd(35): signal a is in statement, but is not in sensitivity list" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_accb.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_accb.vhd" 35 0 0 } }  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "9 " "Info: Ignored 9 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "9 " "Info: Ignored 9 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "FREDEVIDER8:inst8\|COUNTER\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: FREDEVIDER8:inst8\|COUNTER\[0\]~8" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/FREDEVIDER8.vhd" "" "COUNTER\[0\]~8" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/FREDEVIDER8.vhd" 17 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_0b7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_0b7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_0b7 " "Info: Found entity 1: cntr_0b7" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/cntr_0b7.tdf" "cntr_0b7" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/db/cntr_0b7.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer to OR gate or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[6\] " "Warning: Converting TRI node BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[6\] that feeds logic to an OR gate" {  } { { "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[5\] " "Warning: Converting TRI node BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[5\] that feeds logic to an OR gate" {  } { { "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[4\] " "Warning: Converting TRI node BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[4\] that feeds logic to an OR gate" {  } { { "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[3\] " "Warning: Converting TRI node BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[3\] that feeds logic to an OR gate" {  } { { "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[2\] " "Warning: Converting TRI node BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[2\] that feeds logic to an OR gate" {  } { { "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[1\] " "Warning: Converting TRI node BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[1\] that feeds logic to an OR gate" {  } { { "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[0\] " "Warning: Converting TRI node BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[0\] that feeds logic to an OR gate" {  } { { "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[7\] " "Warning: Converting TRI node BUSTRI:inst1\|lpm_bustri:lpm_bustri_component\|din\[7\] that feeds logic to an OR gate" {  } { { "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "XFER GND " "Warning: Pin XFER stuck at GND" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 440 1280 1456 456 "XFER" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "DA1CS GND " "Warning: Pin DA1CS stuck at GND" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 392 1280 1456 408 "DA1CS" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "DA2CS GND " "Warning: Pin DA2CS stuck at GND" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 408 1280 1456 424 "DA2CS" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "WRN GND " "Warning: Pin WRN stuck at GND" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 424 1280 1456 440 "WRN" "" } } } }  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "5 " "Warning: Design contains 5 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "P2\[4\] " "Warning: No output dependent on input pin P2\[4\]" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 424 104 272 440 "P2\[4..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "P2\[3\] " "Warning: No output dependent on input pin P2\[3\]" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 424 104 272 440 "P2\[4..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "P2\[2\] " "Warning: No output dependent on input pin P2\[2\]" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 424 104 272 440 "P2\[4..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "P2\[1\] " "Warning: No output dependent on input pin P2\[1\]" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 424 104 272 440 "P2\[4..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "P2\[0\] " "Warning: No output dependent on input pin P2\[0\]" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 424 104 272 440 "P2\[4..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "157 " "Info: Implemented 157 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "20 " "Info: Implemented 20 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "111 " "Info: Implemented 111 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 21 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 24 18:30:12 2005 " "Info: Processing ended: Wed Aug 24 18:30:12 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}