test_double3.tan.qmsg

DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫屏锯齿波。频率可用键盘精确控制

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK P0\[7\] BUS_51:inst9\|P0_OUT\[7\] 6.457 ns register " "Info: Minimum tco from clock CLK to destination pin P0\[7\] through register BUS_51:inst9\|P0_OUT\[7\] is 6.457 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.721 ns + Shortest register " "Info: + Shortest clock path from clock CLK to source register is 2.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 57 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 57; CLK Node = 'CLK'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 96 88 256 112 "CLK" "" } { 88 256 312 104 "CLK" "" } { 224 1024 1048 240 "CLK" "" } { 400 328 368 416 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.711 ns) 2.721 ns BUS_51:inst9\|P0_OUT\[7\] 2 REG LC_X21_Y3_N3 2 " "Info: 2: + IC(0.541 ns) + CELL(0.711 ns) = 2.721 ns; Loc. = LC_X21_Y3_N3; Fanout = 2; REG Node = 'BUS_51:inst9\|P0_OUT\[7\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.252 ns" { CLK BUS_51:inst9|P0_OUT[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 80.12 % " "Info: Total cell delay = 2.180 ns ( 80.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.88 % " "Info: Total interconnect delay = 0.541 ns ( 19.88 % )" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "2.721 ns" { CLK BUS_51:inst9|P0_OUT[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.512 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.512 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BUS_51:inst9\|P0_OUT\[7\] 1 REG LC_X21_Y3_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y3_N3; Fanout = 2; REG Node = 'BUS_51:inst9\|P0_OUT\[7\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { BUS_51:inst9|P0_OUT[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.404 ns) + CELL(2.108 ns) 3.512 ns P0\[7\] 2 PIN PIN_68 0 " "Info: 2: + IC(1.404 ns) + CELL(2.108 ns) = 3.512 ns; Loc. = PIN_68; Fanout = 0; PIN Node = 'P0\[7\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "3.512 ns" { BUS_51:inst9|P0_OUT[7] P0[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 216 88 264 232 "P0\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 60.02 % " "Info: Total cell delay = 2.108 ns ( 60.02 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.404 ns 39.98 % " "Info: Total interconnect delay = 1.404 ns ( 39.98 % )" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "3.512 ns" { BUS_51:inst9|P0_OUT[7] P0[7] } "NODE_NAME" } } }  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "2.721 ns" { CLK BUS_51:inst9|P0_OUT[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "3.512 ns" { BUS_51:inst9|P0_OUT[7] P0[7] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 24 18:30:25 2005 " "Info: Processing ended: Wed Aug 24 18:30:25 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}