test_double3.tan.qmsg

DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫屏锯齿波。频率可用键盘精确控制

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "BUS_51:inst9\|RAMTMP0\[7\] generator_accB:inst3\|REG_Q\[15\] CLK 2.403 ns " "Info: Found hold time violation between source  pin or register BUS_51:inst9\|RAMTMP0\[7\] and destination pin or register generator_accB:inst3\|REG_Q\[15\] for clock CLK (Hold time is 2.403 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.102 ns + Largest " "Info: + Largest clock skew is 4.102 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.823 ns + Longest register " "Info: + Longest clock path from clock CLK to destination register is 6.823 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 57 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 57; CLK Node = 'CLK'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 96 88 256 112 "CLK" "" } { 88 256 312 104 "CLK" "" } { 224 1024 1048 240 "CLK" "" } { 400 328 368 416 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.537 ns) + CELL(0.935 ns) 2.941 ns FREDEVIDER8:inst8\|CLK 2 REG LC_X8_Y6_N2 42 " "Info: 2: + IC(0.537 ns) + CELL(0.935 ns) = 2.941 ns; Loc. = LC_X8_Y6_N2; Fanout = 42; REG Node = 'FREDEVIDER8:inst8\|CLK'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.472 ns" { CLK FREDEVIDER8:inst8|CLK } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/FREDEVIDER8.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/FREDEVIDER8.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.171 ns) + CELL(0.711 ns) 6.823 ns generator_accB:inst3\|REG_Q\[15\] 3 REG LC_X18_Y4_N7 3 " "Info: 3: + IC(3.171 ns) + CELL(0.711 ns) = 6.823 ns; Loc. = LC_X18_Y4_N7; Fanout = 3; REG Node = 'generator_accB:inst3\|REG_Q\[15\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "3.882 ns" { FREDEVIDER8:inst8|CLK generator_accB:inst3|REG_Q[15] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_accb.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_accb.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 45.65 % " "Info: Total cell delay = 3.115 ns ( 45.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.708 ns 54.35 % " "Info: Total interconnect delay = 3.708 ns ( 54.35 % )" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "6.823 ns" { CLK FREDEVIDER8:inst8|CLK generator_accB:inst3|REG_Q[15] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.721 ns - Shortest register " "Info: - Shortest clock path from clock CLK to source register is 2.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 57 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 57; CLK Node = 'CLK'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 96 88 256 112 "CLK" "" } { 88 256 312 104 "CLK" "" } { 224 1024 1048 240 "CLK" "" } { 400 328 368 416 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.711 ns) 2.721 ns BUS_51:inst9\|RAMTMP0\[7\] 2 REG LC_X21_Y4_N5 3 " "Info: 2: + IC(0.541 ns) + CELL(0.711 ns) = 2.721 ns; Loc. = LC_X21_Y4_N5; Fanout = 3; REG Node = 'BUS_51:inst9\|RAMTMP0\[7\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.252 ns" { CLK BUS_51:inst9|RAMTMP0[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 80.12 % " "Info: Total cell delay = 2.180 ns ( 80.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.88 % " "Info: Total interconnect delay = 0.541 ns ( 19.88 % )" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "2.721 ns" { CLK BUS_51:inst9|RAMTMP0[7] } "NODE_NAME" } } }  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "6.823 ns" { CLK FREDEVIDER8:inst8|CLK generator_accB:inst3|REG_Q[15] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "2.721 ns" { CLK BUS_51:inst9|RAMTMP0[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.490 ns - Shortest register register " "Info: - Shortest register to register delay is 1.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BUS_51:inst9\|RAMTMP0\[7\] 1 REG LC_X21_Y4_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y4_N5; Fanout = 3; REG Node = 'BUS_51:inst9\|RAMTMP0\[7\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { BUS_51:inst9|RAMTMP0[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.181 ns) + CELL(0.309 ns) 1.490 ns generator_accB:inst3\|REG_Q\[15\] 2 REG LC_X18_Y4_N7 3 " "Info: 2: + IC(1.181 ns) + CELL(0.309 ns) = 1.490 ns; Loc. = LC_X18_Y4_N7; Fanout = 3; REG Node = 'generator_accB:inst3\|REG_Q\[15\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.490 ns" { BUS_51:inst9|RAMTMP0[7] generator_accB:inst3|REG_Q[15] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_accb.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_accb.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 20.74 % " "Info: Total cell delay = 0.309 ns ( 20.74 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.181 ns 79.26 % " "Info: Total interconnect delay = 1.181 ns ( 79.26 % )" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.490 ns" { BUS_51:inst9|RAMTMP0[7] generator_accB:inst3|REG_Q[15] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_accb.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_accb.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 53 -1 0 } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_accb.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_accb.vhd" 40 -1 0 } }  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "6.823 ns" { CLK FREDEVIDER8:inst8|CLK generator_accB:inst3|REG_Q[15] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "2.721 ns" { CLK BUS_51:inst9|RAMTMP0[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.490 ns" { BUS_51:inst9|RAMTMP0[7] generator_accB:inst3|REG_Q[15] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "BUS_51:inst9\|RAMTMP3\[7\] WR CLK 7.955 ns register " "Info: tsu for register BUS_51:inst9\|RAMTMP3\[7\] (data pin = WR, clock pin = CLK) is 7.955 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.639 ns + Longest pin register " "Info: + Longest pin to register delay is 10.639 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns WR 1 PIN PIN_77 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_77; Fanout = 3; PIN Node = 'WR'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { WR } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 392 104 272 408 "WR" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.792 ns) + CELL(0.292 ns) 7.553 ns BUS_51:inst9\|process2~0 2 COMB LC_X21_Y4_N2 10 " "Info: 2: + IC(5.792 ns) + CELL(0.292 ns) = 7.553 ns; Loc. = LC_X21_Y4_N2; Fanout = 10; COMB Node = 'BUS_51:inst9\|process2~0'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "6.084 ns" { WR BUS_51:inst9|process2~0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.292 ns) 8.621 ns BUS_51:inst9\|RAMTMP3\[7\]~16 3 COMB LC_X20_Y4_N7 1 " "Info: 3: + IC(0.776 ns) + CELL(0.292 ns) = 8.621 ns; Loc. = LC_X20_Y4_N7; Fanout = 1; COMB Node = 'BUS_51:inst9\|RAMTMP3\[7\]~16'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.068 ns" { BUS_51:inst9|process2~0 BUS_51:inst9|RAMTMP3[7]~16 } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.151 ns) + CELL(0.867 ns) 10.639 ns BUS_51:inst9\|RAMTMP3\[7\] 4 REG LC_X20_Y4_N4 4 " "Info: 4: + IC(1.151 ns) + CELL(0.867 ns) = 10.639 ns; Loc. = LC_X20_Y4_N4; Fanout = 4; REG Node = 'BUS_51:inst9\|RAMTMP3\[7\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "2.018 ns" { BUS_51:inst9|RAMTMP3[7]~16 BUS_51:inst9|RAMTMP3[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.920 ns 27.45 % " "Info: Total cell delay = 2.920 ns ( 27.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.719 ns 72.55 % " "Info: Total interconnect delay = 7.719 ns ( 72.55 % )" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "10.639 ns" { WR BUS_51:inst9|process2~0 BUS_51:inst9|RAMTMP3[7]~16 BUS_51:inst9|RAMTMP3[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.721 ns - Shortest register " "Info: - Shortest clock path from clock CLK to destination register is 2.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 57 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 57; CLK Node = 'CLK'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 96 88 256 112 "CLK" "" } { 88 256 312 104 "CLK" "" } { 224 1024 1048 240 "CLK" "" } { 400 328 368 416 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.711 ns) 2.721 ns BUS_51:inst9\|RAMTMP3\[7\] 2 REG LC_X20_Y4_N4 4 " "Info: 2: + IC(0.541 ns) + CELL(0.711 ns) = 2.721 ns; Loc. = LC_X20_Y4_N4; Fanout = 4; REG Node = 'BUS_51:inst9\|RAMTMP3\[7\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.252 ns" { CLK BUS_51:inst9|RAMTMP3[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 80.12 % " "Info: Total cell delay = 2.180 ns ( 80.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.88 % " "Info: Total interconnect delay = 0.541 ns ( 19.88 % )" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "2.721 ns" { CLK BUS_51:inst9|RAMTMP3[7] } "NODE_NAME" } } }  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "10.639 ns" { WR BUS_51:inst9|process2~0 BUS_51:inst9|RAMTMP3[7]~16 BUS_51:inst9|RAMTMP3[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "2.721 ns" { CLK BUS_51:inst9|RAMTMP3[7] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q1\[7\] generator_reg81:inst6\|TEMP_Q_1\[7\] 11.464 ns register " "Info: tco from clock CLK to destination pin Q1\[7\] through register generator_reg81:inst6\|TEMP_Q_1\[7\] is 11.464 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 6.810 ns + Longest register " "Info: + Longest clock path from clock CLK to source register is 6.810 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 57 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 57; CLK Node = 'CLK'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 96 88 256 112 "CLK" "" } { 88 256 312 104 "CLK" "" } { 224 1024 1048 240 "CLK" "" } { 400 328 368 416 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.537 ns) + CELL(0.935 ns) 2.941 ns FREDEVIDER8:inst8\|CLK 2 REG LC_X8_Y6_N2 42 " "Info: 2: + IC(0.537 ns) + CELL(0.935 ns) = 2.941 ns; Loc. = LC_X8_Y6_N2; Fanout = 42; REG Node = 'FREDEVIDER8:inst8\|CLK'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.472 ns" { CLK FREDEVIDER8:inst8|CLK } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/FREDEVIDER8.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/FREDEVIDER8.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.158 ns) + CELL(0.711 ns) 6.810 ns generator_reg81:inst6\|TEMP_Q_1\[7\] 3 REG LC_X12_Y2_N2 1 " "Info: 3: + IC(3.158 ns) + CELL(0.711 ns) = 6.810 ns; Loc. = LC_X12_Y2_N2; Fanout = 1; REG Node = 'generator_reg81:inst6\|TEMP_Q_1\[7\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "3.869 ns" { FREDEVIDER8:inst8|CLK generator_reg81:inst6|TEMP_Q_1[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_reg81.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_reg81.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 45.74 % " "Info: Total cell delay = 3.115 ns ( 45.74 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.695 ns 54.26 % " "Info: Total interconnect delay = 3.695 ns ( 54.26 % )" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "6.810 ns" { CLK FREDEVIDER8:inst8|CLK generator_reg81:inst6|TEMP_Q_1[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_reg81.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_reg81.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.430 ns + Longest register pin " "Info: + Longest register to pin delay is 4.430 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns generator_reg81:inst6\|TEMP_Q_1\[7\] 1 REG LC_X12_Y2_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y2_N2; Fanout = 1; REG Node = 'generator_reg81:inst6\|TEMP_Q_1\[7\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { generator_reg81:inst6|TEMP_Q_1[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_reg81.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/generator_reg81.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.322 ns) + CELL(2.108 ns) 4.430 ns Q1\[7\] 2 PIN PIN_38 0 " "Info: 2: + IC(2.322 ns) + CELL(2.108 ns) = 4.430 ns; Loc. = PIN_38; Fanout = 0; PIN Node = 'Q1\[7\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "4.430 ns" { generator_reg81:inst6|TEMP_Q_1[7] Q1[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 192 1480 1656 208 "Q1\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 47.58 % " "Info: Total cell delay = 2.108 ns ( 47.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.322 ns 52.42 % " "Info: Total interconnect delay = 2.322 ns ( 52.42 % )" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "4.430 ns" { generator_reg81:inst6|TEMP_Q_1[7] Q1[7] } "NODE_NAME" } } }  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "6.810 ns" { CLK FREDEVIDER8:inst8|CLK generator_reg81:inst6|TEMP_Q_1[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "4.430 ns" { generator_reg81:inst6|TEMP_Q_1[7] Q1[7] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "BUS_51:inst9\|LATCH_ADDRES\[0\] P0\[0\] ALE 3.179 ns register " "Info: th for register BUS_51:inst9\|LATCH_ADDRES\[0\] (data pin = P0\[0\], clock pin = ALE) is 3.179 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ALE destination 10.097 ns + Longest register " "Info: + Longest clock path from clock ALE to destination register is 10.097 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ALE 1 CLK PIN_78 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_78; Fanout = 8; CLK Node = 'ALE'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { ALE } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 360 104 272 376 "ALE" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.917 ns) + CELL(0.711 ns) 10.097 ns BUS_51:inst9\|LATCH_ADDRES\[0\] 2 REG LC_X20_Y2_N8 5 " "Info: 2: + IC(7.917 ns) + CELL(0.711 ns) = 10.097 ns; Loc. = LC_X20_Y2_N8; Fanout = 5; REG Node = 'BUS_51:inst9\|LATCH_ADDRES\[0\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "8.628 ns" { ALE BUS_51:inst9|LATCH_ADDRES[0] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 21.59 % " "Info: Total cell delay = 2.180 ns ( 21.59 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.917 ns 78.41 % " "Info: Total interconnect delay = 7.917 ns ( 78.41 % )" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "10.097 ns" { ALE BUS_51:inst9|LATCH_ADDRES[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.933 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.933 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns P0\[0\] 1 PIN PIN_75 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_75; Fanout = 1; PIN Node = 'P0\[0\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { P0[0] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 216 88 264 232 "P0\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns P0~7 2 COMB IOC_X27_Y2_N1 4 " "Info: 2: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = IOC_X27_Y2_N1; Fanout = 4; COMB Node = 'P0~7'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.469 ns" { P0[0] P0~7 } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 216 88 264 232 "P0\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.349 ns) + CELL(0.115 ns) 6.933 ns BUS_51:inst9\|LATCH_ADDRES\[0\] 3 REG LC_X20_Y2_N8 5 " "Info: 3: + IC(5.349 ns) + CELL(0.115 ns) = 6.933 ns; Loc. = LC_X20_Y2_N8; Fanout = 5; REG Node = 'BUS_51:inst9\|LATCH_ADDRES\[0\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "5.464 ns" { P0~7 BUS_51:inst9|LATCH_ADDRES[0] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns 22.85 % " "Info: Total cell delay = 1.584 ns ( 22.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.349 ns 77.15 % " "Info: Total interconnect delay = 5.349 ns ( 77.15 % )" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "6.933 ns" { P0[0] P0~7 BUS_51:inst9|LATCH_ADDRES[0] } "NODE_NAME" } } }  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "10.097 ns" { ALE BUS_51:inst9|LATCH_ADDRES[0] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "6.933 ns" { P0[0] P0~7 BUS_51:inst9|LATCH_ADDRES[0] } "NODE_NAME" } } }  } 0}