test_double3.tan.qmsg

DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫屏锯齿波。频率可用键盘精确控制

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "FREDEVIDER8:inst8\|CLK " "Info: Detected ripple clock FREDEVIDER8:inst8\|CLK as buffer" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/FREDEVIDER8.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/FREDEVIDER8.vhd" 17 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "FREDEVIDER8:inst8\|CLK" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register BUS_51:inst9\|RAMTMP3\[7\] memory lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_uou:auto_generated\|ram_block1a7~porta_address_reg7 92.03 MHz 10.866 ns Internal " "Info: Clock CLK has Internal fmax of 92.03 MHz between source register BUS_51:inst9\|RAMTMP3\[7\] and destination memory lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_uou:auto_generated\|ram_block1a7~porta_address_reg7 (period= 10.866 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.127 ns + Longest register memory " "Info: + Longest register to memory delay is 5.127 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BUS_51:inst9\|RAMTMP3\[7\] 1 REG LC_X20_Y4_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y4_N4; Fanout = 4; REG Node = 'BUS_51:inst9\|RAMTMP3\[7\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { BUS_51:inst9|RAMTMP3[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.750 ns) + CELL(0.423 ns) 1.173 ns generator_add:inst4\|add~2COUT0 2 COMB LC_X19_Y4_N0 2 " "Info: 2: + IC(0.750 ns) + CELL(0.423 ns) = 1.173 ns; Loc. = LC_X19_Y4_N0; Fanout = 2; COMB Node = 'generator_add:inst4\|add~2COUT0'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.173 ns" { BUS_51:inst9|RAMTMP3[7] generator_add:inst4|add~2COUT0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.251 ns generator_add:inst4\|add~3COUT0 3 COMB LC_X19_Y4_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.251 ns; Loc. = LC_X19_Y4_N1; Fanout = 2; COMB Node = 'generator_add:inst4\|add~3COUT0'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "0.078 ns" { generator_add:inst4|add~2COUT0 generator_add:inst4|add~3COUT0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.329 ns generator_add:inst4\|add~4COUT0 4 COMB LC_X19_Y4_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.329 ns; Loc. = LC_X19_Y4_N2; Fanout = 2; COMB Node = 'generator_add:inst4\|add~4COUT0'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "0.078 ns" { generator_add:inst4|add~3COUT0 generator_add:inst4|add~4COUT0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.407 ns generator_add:inst4\|add~5COUT0 5 COMB LC_X19_Y4_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 1.407 ns; Loc. = LC_X19_Y4_N3; Fanout = 2; COMB Node = 'generator_add:inst4\|add~5COUT0'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "0.078 ns" { generator_add:inst4|add~4COUT0 generator_add:inst4|add~5COUT0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.585 ns generator_add:inst4\|add~6COUT 6 COMB LC_X19_Y4_N4 4 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 1.585 ns; Loc. = LC_X19_Y4_N4; Fanout = 4; COMB Node = 'generator_add:inst4\|add~6COUT'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "0.178 ns" { generator_add:inst4|add~5COUT0 generator_add:inst4|add~6COUT } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.206 ns generator_add:inst4\|add~9 7 COMB LC_X19_Y4_N7 1 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 2.206 ns; Loc. = LC_X19_Y4_N7; Fanout = 1; COMB Node = 'generator_add:inst4\|add~9'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "0.621 ns" { generator_add:inst4|add~6COUT generator_add:inst4|add~9 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.114 ns) 3.409 ns generator_add:inst4\|add~54 8 COMB LC_X17_Y4_N4 1 " "Info: 8: + IC(1.089 ns) + CELL(0.114 ns) = 3.409 ns; Loc. = LC_X17_Y4_N4; Fanout = 1; COMB Node = 'generator_add:inst4\|add~54'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.203 ns" { generator_add:inst4|add~9 generator_add:inst4|add~54 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.335 ns) + CELL(0.383 ns) 5.127 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_uou:auto_generated\|ram_block1a7~porta_address_reg7 9 MEM M4K_X13_Y4 8 " "Info: 9: + IC(1.335 ns) + CELL(0.383 ns) = 5.127 ns; Loc. = M4K_X13_Y4; Fanout = 8; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_uou:auto_generated\|ram_block1a7~porta_address_reg7'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.718 ns" { generator_add:inst4|add~54 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_uou:auto_generated|ram_block1a7~porta_address_reg7 } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/altsyncram_uou.tdf" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/db/altsyncram_uou.tdf" 171 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.953 ns 38.09 % " "Info: Total cell delay = 1.953 ns ( 38.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.174 ns 61.91 % " "Info: Total interconnect delay = 3.174 ns ( 61.91 % )" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "5.127 ns" { BUS_51:inst9|RAMTMP3[7] generator_add:inst4|add~2COUT0 generator_add:inst4|add~3COUT0 generator_add:inst4|add~4COUT0 generator_add:inst4|add~5COUT0 generator_add:inst4|add~6COUT generator_add:inst4|add~9 generator_add:inst4|add~54 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_uou:auto_generated|ram_block1a7~porta_address_reg7 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.011 ns - Smallest " "Info: - Smallest clock skew is 0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.732 ns + Shortest memory " "Info: + Shortest clock path from clock CLK to destination memory is 2.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 57 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 57; CLK Node = 'CLK'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 96 88 256 112 "CLK" "" } { 88 256 312 104 "CLK" "" } { 224 1024 1048 240 "CLK" "" } { 400 328 368 416 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.722 ns) 2.732 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_uou:auto_generated\|ram_block1a7~porta_address_reg7 2 MEM M4K_X13_Y4 8 " "Info: 2: + IC(0.541 ns) + CELL(0.722 ns) = 2.732 ns; Loc. = M4K_X13_Y4; Fanout = 8; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_uou:auto_generated\|ram_block1a7~porta_address_reg7'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.263 ns" { CLK lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_uou:auto_generated|ram_block1a7~porta_address_reg7 } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/altsyncram_uou.tdf" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/db/altsyncram_uou.tdf" 171 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 80.20 % " "Info: Total cell delay = 2.191 ns ( 80.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.80 % " "Info: Total interconnect delay = 0.541 ns ( 19.80 % )" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "2.732 ns" { CLK lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_uou:auto_generated|ram_block1a7~porta_address_reg7 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.721 ns - Longest register " "Info: - Longest clock path from clock CLK to source register is 2.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 57 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 57; CLK Node = 'CLK'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 96 88 256 112 "CLK" "" } { 88 256 312 104 "CLK" "" } { 224 1024 1048 240 "CLK" "" } { 400 328 368 416 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.711 ns) 2.721 ns BUS_51:inst9\|RAMTMP3\[7\] 2 REG LC_X20_Y4_N4 4 " "Info: 2: + IC(0.541 ns) + CELL(0.711 ns) = 2.721 ns; Loc. = LC_X20_Y4_N4; Fanout = 4; REG Node = 'BUS_51:inst9\|RAMTMP3\[7\]'" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "1.252 ns" { CLK BUS_51:inst9|RAMTMP3[7] } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 80.12 % " "Info: Total cell delay = 2.180 ns ( 80.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.88 % " "Info: Total interconnect delay = 0.541 ns ( 19.88 % )" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "2.721 ns" { CLK BUS_51:inst9|RAMTMP3[7] } "NODE_NAME" } } }  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "2.732 ns" { CLK lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_uou:auto_generated|ram_block1a7~porta_address_reg7 } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "2.721 ns" { CLK BUS_51:inst9|RAMTMP3[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/altsyncram_uou.tdf" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/db/altsyncram_uou.tdf" 171 2 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 53 -1 0 } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/altsyncram_uou.tdf" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/db/altsyncram_uou.tdf" 171 2 0 } }  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "5.127 ns" { BUS_51:inst9|RAMTMP3[7] generator_add:inst4|add~2COUT0 generator_add:inst4|add~3COUT0 generator_add:inst4|add~4COUT0 generator_add:inst4|add~5COUT0 generator_add:inst4|add~6COUT generator_add:inst4|add~9 generator_add:inst4|add~54 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_uou:auto_generated|ram_block1a7~porta_address_reg7 } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "2.732 ns" { CLK lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_uou:auto_generated|ram_block1a7~porta_address_reg7 } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "2.721 ns" { CLK BUS_51:inst9|RAMTMP3[7] } "NODE_NAME" } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "ALE " "Info: No valid register-to-register paths exist for clock ALE" {  } {  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK 152 " "Warning: Circuit may not operate. Detected 152 non-operational path(s) clocked by clock CLK with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}