test_double3.map.eqn

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--G1_TEMP_Q_1[7] is generator_reg81:inst6|TEMP_Q_1[7]
--operation mode is normal

G1_TEMP_Q_1[7]_lut_out = M1_q_a[7];
G1_TEMP_Q_1[7] = DFFEA(G1_TEMP_Q_1[7]_lut_out, J1_CLK, !K1_TMP, , , , );


--G1_TEMP_Q_1[6] is generator_reg81:inst6|TEMP_Q_1[6]
--operation mode is normal

G1_TEMP_Q_1[6]_lut_out = M1_q_a[6];
G1_TEMP_Q_1[6] = DFFEA(G1_TEMP_Q_1[6]_lut_out, J1_CLK, !K1_TMP, , , , );


--G1_TEMP_Q_1[5] is generator_reg81:inst6|TEMP_Q_1[5]
--operation mode is normal

G1_TEMP_Q_1[5]_lut_out = M1_q_a[5];
G1_TEMP_Q_1[5] = DFFEA(G1_TEMP_Q_1[5]_lut_out, J1_CLK, !K1_TMP, , , , );


--G1_TEMP_Q_1[4] is generator_reg81:inst6|TEMP_Q_1[4]
--operation mode is normal

G1_TEMP_Q_1[4]_lut_out = M1_q_a[4];
G1_TEMP_Q_1[4] = DFFEA(G1_TEMP_Q_1[4]_lut_out, J1_CLK, !K1_TMP, , , , );


--G1_TEMP_Q_1[3] is generator_reg81:inst6|TEMP_Q_1[3]
--operation mode is normal

G1_TEMP_Q_1[3]_lut_out = M1_q_a[3];
G1_TEMP_Q_1[3] = DFFEA(G1_TEMP_Q_1[3]_lut_out, J1_CLK, !K1_TMP, , , , );


--G1_TEMP_Q_1[2] is generator_reg81:inst6|TEMP_Q_1[2]
--operation mode is normal

G1_TEMP_Q_1[2]_lut_out = M1_q_a[2];
G1_TEMP_Q_1[2] = DFFEA(G1_TEMP_Q_1[2]_lut_out, J1_CLK, !K1_TMP, , , , );


--G1_TEMP_Q_1[1] is generator_reg81:inst6|TEMP_Q_1[1]
--operation mode is normal

G1_TEMP_Q_1[1]_lut_out = M1_q_a[1];
G1_TEMP_Q_1[1] = DFFEA(G1_TEMP_Q_1[1]_lut_out, J1_CLK, !K1_TMP, , , , );


--G1_TEMP_Q_1[0] is generator_reg81:inst6|TEMP_Q_1[0]
--operation mode is normal

G1_TEMP_Q_1[0]_lut_out = M1_q_a[0];
G1_TEMP_Q_1[0] = DFFEA(G1_TEMP_Q_1[0]_lut_out, J1_CLK, !K1_TMP, , , , );


--H1_TEMP_Q_1[7] is generator_reg82:inst7|TEMP_Q_1[7]
--operation mode is normal

H1_TEMP_Q_1[7]_lut_out = M1_q_a[7];
H1_TEMP_Q_1[7] = DFFEA(H1_TEMP_Q_1[7]_lut_out, !J1_CLK, !K1_TMP, , , , );


--H1_TEMP_Q_1[6] is generator_reg82:inst7|TEMP_Q_1[6]
--operation mode is normal

H1_TEMP_Q_1[6]_lut_out = M1_q_a[6];
H1_TEMP_Q_1[6] = DFFEA(H1_TEMP_Q_1[6]_lut_out, !J1_CLK, !K1_TMP, , , , );


--H1_TEMP_Q_1[5] is generator_reg82:inst7|TEMP_Q_1[5]
--operation mode is normal

H1_TEMP_Q_1[5]_lut_out = M1_q_a[5];
H1_TEMP_Q_1[5] = DFFEA(H1_TEMP_Q_1[5]_lut_out, !J1_CLK, !K1_TMP, , , , );


--H1_TEMP_Q_1[4] is generator_reg82:inst7|TEMP_Q_1[4]
--operation mode is normal

H1_TEMP_Q_1[4]_lut_out = M1_q_a[4];
H1_TEMP_Q_1[4] = DFFEA(H1_TEMP_Q_1[4]_lut_out, !J1_CLK, !K1_TMP, , , , );


--H1_TEMP_Q_1[3] is generator_reg82:inst7|TEMP_Q_1[3]
--operation mode is normal

H1_TEMP_Q_1[3]_lut_out = M1_q_a[3];
H1_TEMP_Q_1[3] = DFFEA(H1_TEMP_Q_1[3]_lut_out, !J1_CLK, !K1_TMP, , , , );


--H1_TEMP_Q_1[2] is generator_reg82:inst7|TEMP_Q_1[2]
--operation mode is normal

H1_TEMP_Q_1[2]_lut_out = M1_q_a[2];
H1_TEMP_Q_1[2] = DFFEA(H1_TEMP_Q_1[2]_lut_out, !J1_CLK, !K1_TMP, , , , );


--H1_TEMP_Q_1[1] is generator_reg82:inst7|TEMP_Q_1[1]
--operation mode is normal

H1_TEMP_Q_1[1]_lut_out = M1_q_a[1];
H1_TEMP_Q_1[1] = DFFEA(H1_TEMP_Q_1[1]_lut_out, !J1_CLK, !K1_TMP, , , , );


--H1_TEMP_Q_1[0] is generator_reg82:inst7|TEMP_Q_1[0]
--operation mode is normal

H1_TEMP_Q_1[0]_lut_out = M1_q_a[0];
H1_TEMP_Q_1[0] = DFFEA(H1_TEMP_Q_1[0]_lut_out, !J1_CLK, !K1_TMP, , , , );


--M1_q_a[7] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
M1_q_a[7]_PORT_A_address = BUS(E1L81, E1L91, E1L02, E1L12, E1L22, E1L32, E1L42, E1L52, E1L62);
M1_q_a[7]_PORT_A_address_reg = DFFE(M1_q_a[7]_PORT_A_address, M1_q_a[7]_clock_0, , , );
M1_q_a[7]_clock_0 = CLK;
M1_q_a[7]_PORT_A_data_out = MEMORY(, , M1_q_a[7]_PORT_A_address_reg, , , , , , M1_q_a[7]_clock_0, , , , , );
M1_q_a[7]_PORT_A_data_out_reg = DFFE(M1_q_a[7]_PORT_A_data_out, M1_q_a[7]_clock_0, , , );
M1_q_a[7] = M1_q_a[7]_PORT_A_data_out_reg[0];


--J1_CLK is FREDEVIDER8:inst8|CLK
--operation mode is normal

J1_CLK_lut_out = !J1_CLK;
J1_CLK = DFFEA(J1_CLK_lut_out, CLK, VCC, , J1L2, , );


--K1_TMP is BUS_51:inst9|TMP
--operation mode is normal

K1_TMP_lut_out = K1_LATCH_ADDRES[2] & !K1L06 & (K1_TMP # !K1L85) # !K1_LATCH_ADDRES[2] & (K1_TMP # !K1L85);
K1_TMP = DFFEA(K1_TMP_lut_out, !CLK, VCC, , K1L12, , );


--M1_q_a[6] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
M1_q_a[6]_PORT_A_address = BUS(E1L81, E1L91, E1L02, E1L12, E1L22, E1L32, E1L42, E1L52, E1L62);
M1_q_a[6]_PORT_A_address_reg = DFFE(M1_q_a[6]_PORT_A_address, M1_q_a[6]_clock_0, , , );
M1_q_a[6]_clock_0 = CLK;
M1_q_a[6]_PORT_A_data_out = MEMORY(, , M1_q_a[6]_PORT_A_address_reg, , , , , , M1_q_a[6]_clock_0, , , , , );
M1_q_a[6]_PORT_A_data_out_reg = DFFE(M1_q_a[6]_PORT_A_data_out, M1_q_a[6]_clock_0, , , );
M1_q_a[6] = M1_q_a[6]_PORT_A_data_out_reg[0];


--M1_q_a[5] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
M1_q_a[5]_PORT_A_address = BUS(E1L81, E1L91, E1L02, E1L12, E1L22, E1L32, E1L42, E1L52, E1L62);
M1_q_a[5]_PORT_A_address_reg = DFFE(M1_q_a[5]_PORT_A_address, M1_q_a[5]_clock_0, , , );
M1_q_a[5]_clock_0 = CLK;
M1_q_a[5]_PORT_A_data_out = MEMORY(, , M1_q_a[5]_PORT_A_address_reg, , , , , , M1_q_a[5]_clock_0, , , , , );
M1_q_a[5]_PORT_A_data_out_reg = DFFE(M1_q_a[5]_PORT_A_data_out, M1_q_a[5]_clock_0, , , );
M1_q_a[5] = M1_q_a[5]_PORT_A_data_out_reg[0];


--M1_q_a[4] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
M1_q_a[4]_PORT_A_address = BUS(E1L81, E1L91, E1L02, E1L12, E1L22, E1L32, E1L42, E1L52, E1L62);
M1_q_a[4]_PORT_A_address_reg = DFFE(M1_q_a[4]_PORT_A_address, M1_q_a[4]_clock_0, , , );
M1_q_a[4]_clock_0 = CLK;
M1_q_a[4]_PORT_A_data_out = MEMORY(, , M1_q_a[4]_PORT_A_address_reg, , , , , , M1_q_a[4]_clock_0, , , , , );
M1_q_a[4]_PORT_A_data_out_reg = DFFE(M1_q_a[4]_PORT_A_data_out, M1_q_a[4]_clock_0, , , );
M1_q_a[4] = M1_q_a[4]_PORT_A_data_out_reg[0];


--M1_q_a[3] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
M1_q_a[3]_PORT_A_address = BUS(E1L81, E1L91, E1L02, E1L12, E1L22, E1L32, E1L42, E1L52, E1L62);
M1_q_a[3]_PORT_A_address_reg = DFFE(M1_q_a[3]_PORT_A_address, M1_q_a[3]_clock_0, , , );
M1_q_a[3]_clock_0 = CLK;
M1_q_a[3]_PORT_A_data_out = MEMORY(, , M1_q_a[3]_PORT_A_address_reg, , , , , , M1_q_a[3]_clock_0, , , , , );
M1_q_a[3]_PORT_A_data_out_reg = DFFE(M1_q_a[3]_PORT_A_data_out, M1_q_a[3]_clock_0, , , );
M1_q_a[3] = M1_q_a[3]_PORT_A_data_out_reg[0];


--M1_q_a[2] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
M1_q_a[2]_PORT_A_address = BUS(E1L81, E1L91, E1L02, E1L12, E1L22, E1L32, E1L42, E1L52, E1L62);
M1_q_a[2]_PORT_A_address_reg = DFFE(M1_q_a[2]_PORT_A_address, M1_q_a[2]_clock_0, , , );
M1_q_a[2]_clock_0 = CLK;
M1_q_a[2]_PORT_A_data_out = MEMORY(, , M1_q_a[2]_PORT_A_address_reg, , , , , , M1_q_a[2]_clock_0, , , , , );
M1_q_a[2]_PORT_A_data_out_reg = DFFE(M1_q_a[2]_PORT_A_data_out, M1_q_a[2]_clock_0, , , );
M1_q_a[2] = M1_q_a[2]_PORT_A_data_out_reg[0];


--M1_q_a[1] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
M1_q_a[1]_PORT_A_address = BUS(E1L81, E1L91, E1L02, E1L12, E1L22, E1L32, E1L42, E1L52, E1L62);
M1_q_a[1]_PORT_A_address_reg = DFFE(M1_q_a[1]_PORT_A_address, M1_q_a[1]_clock_0, , , );
M1_q_a[1]_clock_0 = CLK;
M1_q_a[1]_PORT_A_data_out = MEMORY(, , M1_q_a[1]_PORT_A_address_reg, , , , , , M1_q_a[1]_clock_0, , , , , );
M1_q_a[1]_PORT_A_data_out_reg = DFFE(M1_q_a[1]_PORT_A_data_out, M1_q_a[1]_clock_0, , , );
M1_q_a[1] = M1_q_a[1]_PORT_A_data_out_reg[0];


--M1_q_a[0] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
M1_q_a[0]_PORT_A_address = BUS(E1L81, E1L91, E1L02, E1L12, E1L22, E1L32, E1L42, E1L52, E1L62);
M1_q_a[0]_PORT_A_address_reg = DFFE(M1_q_a[0]_PORT_A_address, M1_q_a[0]_clock_0, , , );
M1_q_a[0]_clock_0 = CLK;
M1_q_a[0]_PORT_A_data_out = MEMORY(, , M1_q_a[0]_PORT_A_address_reg, , , , , , M1_q_a[0]_clock_0, , , , , );
M1_q_a[0]_PORT_A_data_out_reg = DFFE(M1_q_a[0]_PORT_A_data_out, M1_q_a[0]_clock_0, , , );
M1_q_a[0] = M1_q_a[0]_PORT_A_data_out_reg[0];


--E1L1 is generator_add:inst4|add~2
--operation mode is arithmetic

E1L1 = D1_REG_Q[7] $ K1_RAMTMP3[7];

--E1L2 is generator_add:inst4|add~2COUT
--operation mode is arithmetic

E1L2 = CARRY(D1_REG_Q[7] & K1_RAMTMP3[7]);


--D1_REG_Q[7] is generator_accB:inst3|REG_Q[7]
--operation mode is arithmetic

D1_REG_Q[7]_carry_eqn = D1L51;
D1_REG_Q[7]_lut_out = D1_REG_Q[7] $ K1_RAMTMP1[7] $ D1_REG_Q[7]_carry_eqn;
D1_REG_Q[7] = DFFEA(D1_REG_Q[7]_lut_out, J1_CLK, !K1_TMP, , , , );

--D1L71 is generator_accB:inst3|REG_Q[7]~COUT
--operation mode is arithmetic

D1L71 = CARRY(D1_REG_Q[7] & !K1_RAMTMP1[7] & !D1L51 # !D1_REG_Q[7] & (!D1L51 # !K1_RAMTMP1[7]));


--E1L81 is generator_add:inst4|add~47
--operation mode is normal

E1L81 = E1L1 & (D1_REG_Q[7] # J1_CLK) # !E1L1 & D1_REG_Q[7] & !J1_CLK;


--E1L3 is generator_add:inst4|add~3
--operation mode is arithmetic

E1L3_carry_eqn = E1L2;
E1L3 = D1_REG_Q[8] $ K1_RAMTMP2[0] $ E1L3_carry_eqn;

--E1L4 is generator_add:inst4|add~3COUT
--operation mode is arithmetic

E1L4 = CARRY(D1_REG_Q[8] & !K1_RAMTMP2[0] & !E1L2 # !D1_REG_Q[8] & (!E1L2 # !K1_RAMTMP2[0]));


--D1_REG_Q[8] is generator_accB:inst3|REG_Q[8]
--operation mode is arithmetic

D1_REG_Q[8]_carry_eqn = D1L71;
D1_REG_Q[8]_lut_out = D1_REG_Q[8] $ K1_RAMTMP0[0] $ !D1_REG_Q[8]_carry_eqn;
D1_REG_Q[8] = DFFEA(D1_REG_Q[8]_lut_out, J1_CLK, !K1_TMP, , , , );

--D1L91 is generator_accB:inst3|REG_Q[8]~COUT
--operation mode is arithmetic

D1L91 = CARRY(D1_REG_Q[8] & (K1_RAMTMP0[0] # !D1L71) # !D1_REG_Q[8] & K1_RAMTMP0[0] & !D1L71);


--E1L91 is generator_add:inst4|add~48
--operation mode is normal

E1L91 = E1L3 & (D1_REG_Q[8] # J1_CLK) # !E1L3 & D1_REG_Q[8] & !J1_CLK;


--E1L5 is generator_add:inst4|add~4
--operation mode is arithmetic

E1L5_carry_eqn = E1L4;
E1L5 = D1_REG_Q[9] $ K1_RAMTMP2[1] $ !E1L5_carry_eqn;

--E1L6 is generator_add:inst4|add~4COUT
--operation mode is arithmetic

E1L6 = CARRY(D1_REG_Q[9] & (K1_RAMTMP2[1] # !E1L4) # !D1_REG_Q[9] & K1_RAMTMP2[1] & !E1L4);


--D1_REG_Q[9] is generator_accB:inst3|REG_Q[9]
--operation mode is arithmetic

D1_REG_Q[9]_carry_eqn = D1L91;
D1_REG_Q[9]_lut_out = D1_REG_Q[9] $ K1_RAMTMP0[1] $ D1_REG_Q[9]_carry_eqn;
D1_REG_Q[9] = DFFEA(D1_REG_Q[9]_lut_out, J1_CLK, !K1_TMP, , , , );

--D1L12 is generator_accB:inst3|REG_Q[9]~COUT
--operation mode is arithmetic

D1L12 = CARRY(D1_REG_Q[9] & !K1_RAMTMP0[1] & !D1L91 # !D1_REG_Q[9] & (!D1L91 # !K1_RAMTMP0[1]));


--E1L02 is generator_add:inst4|add~49
--operation mode is normal

E1L02 = E1L5 & (D1_REG_Q[9] # J1_CLK) # !E1L5 & D1_REG_Q[9] & !J1_CLK;


--E1L7 is generator_add:inst4|add~5
--operation mode is arithmetic

E1L7_carry_eqn = E1L6;
E1L7 = D1_REG_Q[10] $ K1_RAMTMP2[2] $ E1L7_carry_eqn;

--E1L8 is generator_add:inst4|add~5COUT
--operation mode is arithmetic

E1L8 = CARRY(D1_REG_Q[10] & !K1_RAMTMP2[2] & !E1L6 # !D1_REG_Q[10] & (!E1L6 # !K1_RAMTMP2[2]));


--D1_REG_Q[10] is generator_accB:inst3|REG_Q[10]
--operation mode is arithmetic

D1_REG_Q[10]_carry_eqn = D1L12;
D1_REG_Q[10]_lut_out = D1_REG_Q[10] $ K1_RAMTMP0[2] $ !D1_REG_Q[10]_carry_eqn;
D1_REG_Q[10] = DFFEA(D1_REG_Q[10]_lut_out, J1_CLK, !K1_TMP, , , , );

--D1L32 is generator_accB:inst3|REG_Q[10]~COUT
--operation mode is arithmetic

D1L32 = CARRY(D1_REG_Q[10] & (K1_RAMTMP0[2] # !D1L12) # !D1_REG_Q[10] & K1_RAMTMP0[2] & !D1L12);


--E1L12 is generator_add:inst4|add~50
--operation mode is normal

E1L12 = E1L7 & (D1_REG_Q[10] # J1_CLK) # !E1L7 & D1_REG_Q[10] & !J1_CLK;


--E1L9 is generator_add:inst4|add~6
--operation mode is arithmetic

E1L9_carry_eqn = E1L8;
E1L9 = D1_REG_Q[11] $ K1_RAMTMP2[3] $ !E1L9_carry_eqn;

--E1L01 is generator_add:inst4|add~6COUT
--operation mode is arithmetic

E1L01 = CARRY(D1_REG_Q[11] & (K1_RAMTMP2[3] # !E1L8) # !D1_REG_Q[11] & K1_RAMTMP2[3] & !E1L8);


--D1_REG_Q[11] is generator_accB:inst3|REG_Q[11]
--operation mode is arithmetic

D1_REG_Q[11]_carry_eqn = D1L32;
D1_REG_Q[11]_lut_out = D1_REG_Q[11] $ K1_RAMTMP0[3] $ D1_REG_Q[11]_carry_eqn;
D1_REG_Q[11] = DFFEA(D1_REG_Q[11]_lut_out, J1_CLK, !K1_TMP, , , , );

--D1L52 is generator_accB:inst3|REG_Q[11]~COUT
--operation mode is arithmetic

D1L52 = CARRY(D1_REG_Q[11] & !K1_RAMTMP0[3] & !D1L32 # !D1_REG_Q[11] & (!D1L32 # !K1_RAMTMP0[3]));


--E1L22 is generator_add:inst4|add~51
--operation mode is normal

E1L22 = E1L9 & (D1_REG_Q[11] # J1_CLK) # !E1L9 & D1_REG_Q[11] & !J1_CLK;


--E1L11 is generator_add:inst4|add~7
--operation mode is arithmetic

E1L11_carry_eqn = E1L01;
E1L11 = D1_REG_Q[12] $ K1_RAMTMP2[4] $ E1L11_carry_eqn;

--E1L21 is generator_add:inst4|add~7COUT
--operation mode is arithmetic

E1L21 = CARRY(D1_REG_Q[12] & !K1_RAMTMP2[4] & !E1L01 # !D1_REG_Q[12] & (!E1L01 # !K1_RAMTMP2[4]));


--D1_REG_Q[12] is generator_accB:inst3|REG_Q[12]
--operation mode is arithmetic

D1_REG_Q[12]_carry_eqn = D1L52;
D1_REG_Q[12]_lut_out = D1_REG_Q[12] $ K1_RAMTMP0[4] $ !D1_REG_Q[12]_carry_eqn;
D1_REG_Q[12] = DFFEA(D1_REG_Q[12]_lut_out, J1_CLK, !K1_TMP, , , , );

--D1L72 is generator_accB:inst3|REG_Q[12]~COUT
--operation mode is arithmetic

D1L72 = CARRY(D1_REG_Q[12] & (K1_RAMTMP0[4] # !D1L52) # !D1_REG_Q[12] & K1_RAMTMP0[4] & !D1L52);


--E1L32 is generator_add:inst4|add~52
--operation mode is normal

E1L32 = E1L11 & (D1_REG_Q[12] # J1_CLK) # !E1L11 & D1_REG_Q[12] & !J1_CLK;


--E1L31 is generator_add:inst4|add~8
--operation mode is arithmetic

E1L31_carry_eqn = E1L21;
E1L31 = D1_REG_Q[13] $ K1_RAMTMP2[5] $ !E1L31_carry_eqn;

--E1L41 is generator_add:inst4|add~8COUT
--operation mode is arithmetic

E1L41 = CARRY(D1_REG_Q[13] & (K1_RAMTMP2[5] # !E1L21) # !D1_REG_Q[13] & K1_RAMTMP2[5] & !E1L21);


--D1_REG_Q[13] is generator_accB:inst3|REG_Q[13]
--operation mode is arithmetic

D1_REG_Q[13]_carry_eqn = D1L72;
D1_REG_Q[13]_lut_out = D1_REG_Q[13] $ K1_RAMTMP0[5] $ D1_REG_Q[13]_carry_eqn;