test_double3.hier_info

DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫屏锯齿波。频率可用键盘精确控制

|test_double3
XFER <= <GND>
DA1CS <= <GND>
DA2CS <= <GND>
WRN <= <GND>
P0[0] <= BUSTRI:inst1.tridata[0]
P0[1] <= BUSTRI:inst1.tridata[1]
P0[2] <= BUSTRI:inst1.tridata[2]
P0[3] <= BUSTRI:inst1.tridata[3]
P0[4] <= BUSTRI:inst1.tridata[4]
P0[5] <= BUSTRI:inst1.tridata[5]
P0[6] <= BUSTRI:inst1.tridata[6]
P0[7] <= BUSTRI:inst1.tridata[7]
ALE => BUS_51:inst9.ALE
RD => BUS_51:inst9.RD
WR => BUS_51:inst9.WR
CLK => BUS_51:inst9.CLK
CLK => FREDEVIDER8:inst8.CLKIN
CLK => lpm_rom0:inst.clock
CS => BUS_51:inst9.CS
P2[0] => BUS_51:inst9.P2[0]
P2[1] => BUS_51:inst9.P2[1]
P2[2] => BUS_51:inst9.P2[2]
P2[3] => BUS_51:inst9.P2[3]
P2[4] => BUS_51:inst9.P2[4]
Q1[0] <= generator_reg81:inst6.Q1[0]
Q1[1] <= generator_reg81:inst6.Q1[1]
Q1[2] <= generator_reg81:inst6.Q1[2]
Q1[3] <= generator_reg81:inst6.Q1[3]
Q1[4] <= generator_reg81:inst6.Q1[4]
Q1[5] <= generator_reg81:inst6.Q1[5]
Q1[6] <= generator_reg81:inst6.Q1[6]
Q1[7] <= generator_reg81:inst6.Q1[7]
Q2[0] <= generator_reg82:inst7.Q2[0]
Q2[1] <= generator_reg82:inst7.Q2[1]
Q2[2] <= generator_reg82:inst7.Q2[2]
Q2[3] <= generator_reg82:inst7.Q2[3]
Q2[4] <= generator_reg82:inst7.Q2[4]
Q2[5] <= generator_reg82:inst7.Q2[5]
Q2[6] <= generator_reg82:inst7.Q2[6]
Q2[7] <= generator_reg82:inst7.Q2[7]


|test_double3|BUSTRI:inst1
data[0] => lpm_bustri:lpm_bustri_component.data[0]
data[1] => lpm_bustri:lpm_bustri_component.data[1]
data[2] => lpm_bustri:lpm_bustri_component.data[2]
data[3] => lpm_bustri:lpm_bustri_component.data[3]
data[4] => lpm_bustri:lpm_bustri_component.data[4]
data[5] => lpm_bustri:lpm_bustri_component.data[5]
data[6] => lpm_bustri:lpm_bustri_component.data[6]
data[7] => lpm_bustri:lpm_bustri_component.data[7]
enabledt => lpm_bustri:lpm_bustri_component.enabledt
enabletr => lpm_bustri:lpm_bustri_component.enabletr
tridata[0] <= lpm_bustri:lpm_bustri_component.tridata[0]
tridata[1] <= lpm_bustri:lpm_bustri_component.tridata[1]
tridata[2] <= lpm_bustri:lpm_bustri_component.tridata[2]
tridata[3] <= lpm_bustri:lpm_bustri_component.tridata[3]
tridata[4] <= lpm_bustri:lpm_bustri_component.tridata[4]
tridata[5] <= lpm_bustri:lpm_bustri_component.tridata[5]
tridata[6] <= lpm_bustri:lpm_bustri_component.tridata[6]
tridata[7] <= lpm_bustri:lpm_bustri_component.tridata[7]
result[0] <= lpm_bustri:lpm_bustri_component.result[0]
result[1] <= lpm_bustri:lpm_bustri_component.result[1]
result[2] <= lpm_bustri:lpm_bustri_component.result[2]
result[3] <= lpm_bustri:lpm_bustri_component.result[3]
result[4] <= lpm_bustri:lpm_bustri_component.result[4]
result[5] <= lpm_bustri:lpm_bustri_component.result[5]
result[6] <= lpm_bustri:lpm_bustri_component.result[6]
result[7] <= lpm_bustri:lpm_bustri_component.result[7]


|test_double3|BUSTRI:inst1|lpm_bustri:lpm_bustri_component
tridata[0] <= dout[0]
tridata[1] <= dout[1]
tridata[2] <= dout[2]
tridata[3] <= dout[3]
tridata[4] <= dout[4]
tridata[5] <= dout[5]
tridata[6] <= dout[6]
tridata[7] <= dout[7]
data[0] => dout[0].DATAIN
data[1] => dout[1].DATAIN
data[2] => dout[2].DATAIN
data[3] => dout[3].DATAIN
data[4] => dout[4].DATAIN
data[5] => dout[5].DATAIN
data[6] => dout[6].DATAIN
data[7] => dout[7].DATAIN
enabletr => din[7].OE
enabletr => din[6].OE
enabletr => din[5].OE
enabletr => din[4].OE
enabletr => din[3].OE
enabletr => din[2].OE
enabletr => din[1].OE
enabletr => din[0].OE
enabledt => dout[7].OE
enabledt => dout[6].OE
enabledt => dout[5].OE
enabledt => dout[4].OE
enabledt => dout[3].OE
enabledt => dout[2].OE
enabledt => dout[1].OE
enabledt => dout[0].OE
result[0] <= din[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= din[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= din[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= din[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= din[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= din[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= din[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= din[7].DB_MAX_OUTPUT_PORT_TYPE


|test_double3|BUS_51:inst9
P0I[0] => RAMTMP0~39.DATAB
P0I[0] => RAMTMP1~31.DATAB
P0I[0] => RAMTMP2~23.DATAB
P0I[0] => RAMTMP3~15.DATAB
P0I[0] => LATCH_ADDRES[0].DATAIN
P0I[1] => RAMTMP0~38.DATAB
P0I[1] => RAMTMP1~30.DATAB
P0I[1] => RAMTMP2~22.DATAB
P0I[1] => RAMTMP3~14.DATAB
P0I[1] => LATCH_ADDRES[1].DATAIN
P0I[2] => RAMTMP0~37.DATAB
P0I[2] => RAMTMP1~29.DATAB
P0I[2] => RAMTMP2~21.DATAB
P0I[2] => RAMTMP3~13.DATAB
P0I[2] => LATCH_ADDRES[2].DATAIN
P0I[3] => RAMTMP0~36.DATAB
P0I[3] => RAMTMP1~28.DATAB
P0I[3] => RAMTMP2~20.DATAB
P0I[3] => RAMTMP3~12.DATAB
P0I[3] => LATCH_ADDRES[3].DATAIN
P0I[4] => RAMTMP0~35.DATAB
P0I[4] => RAMTMP1~27.DATAB
P0I[4] => RAMTMP2~19.DATAB
P0I[4] => RAMTMP3~11.DATAB
P0I[4] => LATCH_ADDRES[4].DATAIN
P0I[5] => RAMTMP0~34.DATAB
P0I[5] => RAMTMP1~26.DATAB
P0I[5] => RAMTMP2~18.DATAB
P0I[5] => RAMTMP3~10.DATAB
P0I[5] => LATCH_ADDRES[5].DATAIN
P0I[6] => RAMTMP0~33.DATAB
P0I[6] => RAMTMP1~25.DATAB
P0I[6] => RAMTMP2~17.DATAB
P0I[6] => RAMTMP3~9.DATAB
P0I[6] => LATCH_ADDRES[6].DATAIN
P0I[7] => RAMTMP0~32.DATAB
P0I[7] => RAMTMP1~24.DATAB
P0I[7] => RAMTMP2~16.DATAB
P0I[7] => RAMTMP3~8.DATAB
P0I[7] => LATCH_ADDRES[7].DATAIN
P0T[0] <= P0_OUT[0].DB_MAX_OUTPUT_PORT_TYPE
P0T[1] <= P0_OUT[1].DB_MAX_OUTPUT_PORT_TYPE
P0T[2] <= P0_OUT[2].DB_MAX_OUTPUT_PORT_TYPE
P0T[3] <= P0_OUT[3].DB_MAX_OUTPUT_PORT_TYPE
P0T[4] <= P0_OUT[4].DB_MAX_OUTPUT_PORT_TYPE
P0T[5] <= P0_OUT[5].DB_MAX_OUTPUT_PORT_TYPE
P0T[6] <= P0_OUT[6].DB_MAX_OUTPUT_PORT_TYPE
P0T[7] <= P0_OUT[7].DB_MAX_OUTPUT_PORT_TYPE
ALE => LATCH_ADDRES[6].CLK
ALE => LATCH_ADDRES[5].CLK
ALE => LATCH_ADDRES[4].CLK
ALE => LATCH_ADDRES[3].CLK
ALE => LATCH_ADDRES[2].CLK
ALE => LATCH_ADDRES[1].CLK
ALE => LATCH_ADDRES[0].CLK
ALE => LATCH_ADDRES[7].CLK
RD => process1~0.IN0
WR => process2~0.IN1
CLK => P0_OUT[7].CLK
CLK => P0_OUT[6].CLK
CLK => P0_OUT[5].CLK
CLK => P0_OUT[4].CLK
CLK => P0_OUT[3].CLK
CLK => P0_OUT[2].CLK
CLK => P0_OUT[1].CLK
CLK => P0_OUT[0].CLK
CLK => GX~reg0.CLK
CLK => RAMTMP0[6].CLK
CLK => RAMTMP0[5].CLK
CLK => RAMTMP0[4].CLK
CLK => RAMTMP0[3].CLK
CLK => RAMTMP0[2].CLK
CLK => RAMTMP0[1].CLK
CLK => RAMTMP0[0].CLK
CLK => TMP.CLK
CLK => RAMTMP1[7].CLK
CLK => RAMTMP1[6].CLK
CLK => RAMTMP1[5].CLK
CLK => RAMTMP1[4].CLK
CLK => RAMTMP1[3].CLK
CLK => RAMTMP1[2].CLK
CLK => RAMTMP1[1].CLK
CLK => RAMTMP1[0].CLK
CLK => RAMTMP2[7].CLK
CLK => RAMTMP2[6].CLK
CLK => RAMTMP2[5].CLK
CLK => RAMTMP2[4].CLK
CLK => RAMTMP2[3].CLK
CLK => RAMTMP2[2].CLK
CLK => RAMTMP2[1].CLK
CLK => RAMTMP2[0].CLK
CLK => RAMTMP3[7].CLK
CLK => RAMTMP3[6].CLK
CLK => RAMTMP3[5].CLK
CLK => RAMTMP3[4].CLK
CLK => RAMTMP3[3].CLK
CLK => RAMTMP3[2].CLK
CLK => RAMTMP3[1].CLK
CLK => RAMTMP3[0].CLK
CLK => RAMTMP0[7].CLK
GX <= GX~reg0.DB_MAX_OUTPUT_PORT_TYPE
CLR <= TMP.DB_MAX_OUTPUT_PORT_TYPE
PDATA[0] <= RAMTMP3[0].DB_MAX_OUTPUT_PORT_TYPE
PDATA[1] <= RAMTMP3[1].DB_MAX_OUTPUT_PORT_TYPE
PDATA[2] <= RAMTMP3[2].DB_MAX_OUTPUT_PORT_TYPE
PDATA[3] <= RAMTMP3[3].DB_MAX_OUTPUT_PORT_TYPE
PDATA[4] <= RAMTMP3[4].DB_MAX_OUTPUT_PORT_TYPE
PDATA[5] <= RAMTMP3[5].DB_MAX_OUTPUT_PORT_TYPE
PDATA[6] <= RAMTMP3[6].DB_MAX_OUTPUT_PORT_TYPE
PDATA[7] <= RAMTMP3[7].DB_MAX_OUTPUT_PORT_TYPE
PDATA[8] <= RAMTMP2[0].DB_MAX_OUTPUT_PORT_TYPE
PDATA[9] <= RAMTMP2[1].DB_MAX_OUTPUT_PORT_TYPE
PDATA[10] <= RAMTMP2[2].DB_MAX_OUTPUT_PORT_TYPE
PDATA[11] <= RAMTMP2[3].DB_MAX_OUTPUT_PORT_TYPE
PDATA[12] <= RAMTMP2[4].DB_MAX_OUTPUT_PORT_TYPE
PDATA[13] <= RAMTMP2[5].DB_MAX_OUTPUT_PORT_TYPE
PDATA[14] <= RAMTMP2[6].DB_MAX_OUTPUT_PORT_TYPE
PDATA[15] <= RAMTMP2[7].DB_MAX_OUTPUT_PORT_TYPE
FDATA[0] <= RAMTMP1[0].DB_MAX_OUTPUT_PORT_TYPE
FDATA[1] <= RAMTMP1[1].DB_MAX_OUTPUT_PORT_TYPE
FDATA[2] <= RAMTMP1[2].DB_MAX_OUTPUT_PORT_TYPE
FDATA[3] <= RAMTMP1[3].DB_MAX_OUTPUT_PORT_TYPE
FDATA[4] <= RAMTMP1[4].DB_MAX_OUTPUT_PORT_TYPE
FDATA[5] <= RAMTMP1[5].DB_MAX_OUTPUT_PORT_TYPE
FDATA[6] <= RAMTMP1[6].DB_MAX_OUTPUT_PORT_TYPE
FDATA[7] <= RAMTMP1[7].DB_MAX_OUTPUT_PORT_TYPE
FDATA[8] <= RAMTMP0[0].DB_MAX_OUTPUT_PORT_TYPE
FDATA[9] <= RAMTMP0[1].DB_MAX_OUTPUT_PORT_TYPE
FDATA[10] <= RAMTMP0[2].DB_MAX_OUTPUT_PORT_TYPE
FDATA[11] <= RAMTMP0[3].DB_MAX_OUTPUT_PORT_TYPE
FDATA[12] <= RAMTMP0[4].DB_MAX_OUTPUT_PORT_TYPE
FDATA[13] <= RAMTMP0[5].DB_MAX_OUTPUT_PORT_TYPE
FDATA[14] <= RAMTMP0[6].DB_MAX_OUTPUT_PORT_TYPE
FDATA[15] <= RAMTMP0[7].DB_MAX_OUTPUT_PORT_TYPE
P2[0] => ~NO_FANOUT~
P2[1] => ~NO_FANOUT~
P2[2] => ~NO_FANOUT~
P2[3] => ~NO_FANOUT~
P2[4] => ~NO_FANOUT~
CS => process1~0.IN1
CS => process2~0.IN0


|test_double3|generator_reg81:inst6
CLR => TEMP_Q_1[6].ACLR
CLR => TEMP_Q_1[5].ACLR
CLR => TEMP_Q_1[4].ACLR
CLR => TEMP_Q_1[3].ACLR
CLR => TEMP_Q_1[2].ACLR
CLR => TEMP_Q_1[1].ACLR
CLR => TEMP_Q_1[0].ACLR
CLR => TEMP_Q_1[7].ACLR
CLKK => TEMP_Q_1[6].CLK
CLKK => TEMP_Q_1[5].CLK
CLKK => TEMP_Q_1[4].CLK
CLKK => TEMP_Q_1[3].CLK
CLKK => TEMP_Q_1[2].CLK
CLKK => TEMP_Q_1[1].CLK
CLKK => TEMP_Q_1[0].CLK
CLKK => TEMP_Q_1[7].CLK
DATA[0] => TEMP_Q_1[0].DATAIN
DATA[1] => TEMP_Q_1[1].DATAIN
DATA[2] => TEMP_Q_1[2].DATAIN
DATA[3] => TEMP_Q_1[3].DATAIN
DATA[4] => TEMP_Q_1[4].DATAIN
DATA[5] => TEMP_Q_1[5].DATAIN
DATA[6] => TEMP_Q_1[6].DATAIN
DATA[7] => TEMP_Q_1[7].DATAIN
Q1[0] <= TEMP_Q_1[0].DB_MAX_OUTPUT_PORT_TYPE
Q1[1] <= TEMP_Q_1[1].DB_MAX_OUTPUT_PORT_TYPE
Q1[2] <= TEMP_Q_1[2].DB_MAX_OUTPUT_PORT_TYPE
Q1[3] <= TEMP_Q_1[3].DB_MAX_OUTPUT_PORT_TYPE
Q1[4] <= TEMP_Q_1[4].DB_MAX_OUTPUT_PORT_TYPE
Q1[5] <= TEMP_Q_1[5].DB_MAX_OUTPUT_PORT_TYPE
Q1[6] <= TEMP_Q_1[6].DB_MAX_OUTPUT_PORT_TYPE
Q1[7] <= TEMP_Q_1[7].DB_MAX_OUTPUT_PORT_TYPE


|test_double3|FREDEVIDER8:inst8
CLKIN => COUNTER[2].CLK
CLKIN => COUNTER[1].CLK
CLKIN => COUNTER[0].CLK
CLKIN => CLK.CLK
CLKIN => COUNTER[3].CLK
CLKOUT <= CLK.DB_MAX_OUTPUT_PORT_TYPE


|test_double3|lpm_rom0:inst
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|test_double3|lpm_rom0:inst|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~